Abstract: Various implementations described herein are directed to a device having a charge pump and a capacitor. The charge pump may be configured for coupling between first and second power sources. The capacitor may be configured for coupling between the first power source and an input of the charge pump. In an energy harvest mode, the charge pump may decouple from the first and second power sources, and the first power source may charge the capacitor with a first voltage while the charge pump is decoupled from the first and second power sources. In an energy transfer mode, the charge pump may couple to the capacitor and the second power source to transfer the first voltage from the capacitor to the second power source during discharge of the first voltage from the capacitor.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

Abstract: Various implementations described herein are directed to a device having a charge pump and a capacitor. The charge pump may be configured for coupling between first and second power sources. The capacitor may be configured for coupling between the first power source and an input of the charge pump. In an energy harvest mode, the charge pump may decouple from the first and second power sources, and the first power source may charge the capacitor with a first voltage while the charge pump is decoupled from the first and second power sources. In an energy transfer mode, the charge pump may couple to the capacitor and the second power source to transfer the first voltage from the capacitor to the second power source during discharge of the first voltage from the capacitor.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.

Abstract: A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack comprises at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node.