Abstract: A biasing arrangement for a quasi-complementary output stage having first and second transistors of a first type, where at least one of the transistors is driven by a third transistor of a second type. The inventive biasing arrangement comprises a first circuit for biasing the third transistor and a second circuit having a third circuit for providing an input signal to the first transistor and a fourth circuit for providing the input signal to the first circuit. In a particular implementation, the first circuit is connected between the input terminals of the first and the third transistors. The third circuit is a fourth transistor having a first terminal connected to a first source of supply, a second terminal connected to a source of the input signal and a third terminal connected to a second source of supply. The third terminal of the fourth transistor is connected to the second source of supply via a first resistor.

Abstract: An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. According to a first embodiment, feedback circuits are coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. According to a second embodiment, a single feedback circuit controls the voltage at a first node and the same feedback circuit maintains the voltage level of a second node at a constant level.

Abstract: An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. A feedback circuit is coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. The disclosed circuit eliminates circuit drift and offset voltages resulting from changes in common mode and/or power supply voltages by eliminating the effects of resistive loading on the input stage components.

Abstract: A circuit for providing a constant current and a constant bias voltage is described. The circuit includes two paths coupled between a positive voltage supply +V.sub.S and a negative voltage supply -V.sub.S. Each path inlcudes a Zener diode and a enhancement mode field effect transistor (FET) device (the FET device being coupled in a diode configuration) which are connected in series. Each path of the circuit further includes an FET device and an associated resistor combination, coupled in series with the Zener diode and the diode-coupled FET device. The FET device and the associated resistor function as a current source component. A gate terminal of each FET device of the current source component is coupled across the Zener diode and the diode-coupled FET device of the other circuit path.