Abstract: Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding “I” and “P” frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the “I” frames and “P” frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both “I” and “P” frames (as opposed to only “I” frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding “I” and “P” frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the “I” frames and “P” frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both “I” and “P” frames (as opposed to only “I” frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

Abstract: Loss of decoding time prior to the vertical synchronization signal when motion video is arbitrarily scaled and positioned by placing the frame switch point at the completion of frame decoding and synchronizing the bottom border of the scaled image therewith while maintaining low latency of decoded data. High latency operation is provided only when necessitated by minimal spill buffer capacity and in combination with fractional image size reduction in the decoding path in order to maintain image resolution without requiring additional memory.

Abstract: An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor.

Abstract: A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM.

Abstract: A system and method for transferring data between a single channel unit and multiple asynchronous storage devices. One embodiment of the present invention uses read strobe signals to indicate when the storage devices are to send data over a data bus, and to initiate a validity count-down which indicates when the data on the data bus is valid. When the count-down has completed, the data on the data bus is sampled. Another embodiment further includes checking the data for array parity errors while the data is sent and received to and from the storage devices.

Abstract: A system and method for verifying the integrity of control information and informational data. One embodiment of the present invention verifies the integrity of control information received from a host computer, and verifies the integrity of this information as it is transmitted throughout the present invention. Another embodiment of the present invention contemplates verifying the integrity of informational data sent from a host computer, verifying the integrity of informational data as it is transmitted throughout the present invention, generating a CRC based upon the informational data and control information, and transmitting the informational data, control information and corresponding CRC to a storage device.

Abstract: A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gate in data. The data is then sent to the storage devices in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.