Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: A dual-port semiconductor memory device is formed on a chip and includes a plurality of memory cells arranged in rows and columns, and first and second input/output ports for inputting/outputting data to/from the memory device. Each port includes a data terminal, an input/output circuit for inputting/outputting data from/to the data terminal, a storage buffer connected to the input/output circuit for storing/supplying data from/to the input/output means, and read/write amplifiers connected to the storage buffer for reading data from the memory cell array to the storage buffer and writing data from the storage buffer to the memory cell array. A shared global input/output bus is connected to the read/write amplifiers of the first and second ports, and to the memory cell array.

Abstract: A level shift circuit provided with feedforward control to keep the circuit from latching in a wrong logic state comprises a pair of input transistors acted as a differential amplifier and a pair of output hold transistors coupled to output nodes of the circuit. The feedforward control is performed by a pair of feedforward transistors respectively coupled in parallel to the corresponding output hold transistors, and by a pair of isolation transistors that isolate the output nodes from gates of the respective feedforward transistors.