Abstract: A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact. The pedestal includes a cavity and the feature can include one or more blades that extend from a periphery of the cavity to a central longitudinal axis of the pedestal. The three blades are configured to engage the surface of the contact. The three blades can be positioned within the cavity to provide a 120-degree rotational symmetry about the central longitudinal axis of the pedestal.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: A system for testing functionality of die on a wafer including a plurality of contacts includes a support structure and a plurality of probes mounted to the support structure in an array. A configuration of each of the plurality of probes varies based on a position of the probe within the array to maintain uniform engagement between the plurality of probes and a corresponding plurality of contacts across the array.

Abstract: A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact.

Abstract: A system for testing functionality of die on a wafer including a plurality of contacts includes a support structure and a plurality of probes mounted to the support structure in an array. A configuration of each of the plurality of probes varies based on a position of the probe within the array to maintain uniform engagement between the plurality of probes and a corresponding plurality of contacts across the array.

Abstract: A system for testing functionality of die on a wafer including a plurality of contacts includes a support structure and a plurality of probes mounted to the support structure in an array. A configuration of each of the plurality of probes varies based on a position of the probe within the array to maintain uniform engagement between the plurality of probes and a corresponding plurality of contacts across the array.

Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

Abstract: A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact.

Abstract: A system for testing functionality of die on a wafer including a plurality of contacts includes a support structure and a plurality of probes mounted to the support structure in an array. A configuration of each of the plurality of probes varies based on a position of the probe within the array to maintain uniform engagement between the plurality of probes and a corresponding plurality of contacts across the array.

Abstract: Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Abstract: Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Abstract: According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.

Abstract: Disclosed is an integrated circuit chip test apparatus that has a module test fixture having contact pads that are adapted to make contact with signal input/output pins on an integrated circuit chip being tested. An intermediate banking box is connected to the module text fixture and a tester is connected to the intermediate banking box. The tester includes at least one bank of channels there are more pins on the integrated circuit chip than there are channels in the tester. The intermediate banking box includes switches that are connected between the contact pads and the channels. The switches are adapted to selectively connect a subset of the contact pads to the channels to connect the tester to a subset of pins, thereby allowing the tester to test a portion of the integrated circuit that corresponds to the subset of pins.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burn-in to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.