Abstract: A serial-bit digital processing system uses registers and latches to synchronize samples and justify sign-bits. Nominally each processing block in the system includes a sign extend register preceding an arithmetic element and an output register following the arithmetic element. Input registers of one arithmetic element may merge with output registers of the preceding arithmetic element. Ones of the registers include a serially coupled latch which is selectively controlled to pass serial sample bits or to replicate the sign bit. The respective registers are clocked with one of two clock signals having different numbers of pulses per sample period and the length of the respective registers are selected so that at the terminus of each sample period the bits of each sample in the processing system are appropriately justified.