Abstract: A probe card (8,18) for testing unencapsulated semiconductor devices (7,17) wherein the probe card (8,18) is made from a semiconductor material (10). A plurality of pyramidally shaped conductive protrusions or probe tips (11,41) project from the surface of the probe card (8,18) to mate with electrode pads on an unencapsulated semiconductor device (7,17) to be tested. The probe tips (11,41) are formed using standard etch techniques, hence they can be configured to contact electrode pads that reside on the unencapsulated semiconductor device in either a peripheral or area array. Further, the probe card (8,18) is capable of testing integrated circuits in either wafer or die form.

Abstract: A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0.times.10.sup.16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.

Abstract: A method for electrolessly plating portions of semiconductor devices and the like comprises the steps of providing a first metal having a higher electromotive series than a coating metal, galvanically coupling a second metal to the first metal wherein a portion of the first metal remains exposed and then subjecting the second metal and the exposed portion of the first metal to an electroless coating metal plating solution. The method employs no masks and is ideal for plating small areas such as single ball bonds and limited numbers of ball bonds on a single semiconductor chip.

Abstract: A semiconductor device including a metallurgically compatible unplated package is provided. The package includes a plateless copper alloy die mount area to which a semiconductor die is attached. The semiconductor die is metallized on its mounting surface to provide electrical contact. A metallic solder which is compatible with both the copper alloy and the die metallization joins the die to the die mount area. The package further includes a plateless copper alloy lead portion which is physically joined to the die mount area. The top surface of the semiconductor die is provided with a patterned metallization making electrical contact to selected portions of the die. Electrical contact is made between the top surface die metallization and the lead portion of the package by ultrasonically bonded copper ribbon. The die and interconnecting ribbon is then enclosed by an epoxy encapsulant or by a welded metal cover.

Abstract: A semiconductor device including a metallurgically compatible unplated package is provided. The package includes a plateless copper alloy die mount area to which a semiconductor die is attached. The semiconductor die is metallized on its mounting surface to provide electrical contact. A metallic solder which is compatible with both the copper alloy and the die metallization joins the die to the die mount area. The package further includes a plateless copper alloy lead portion which is physically joined to the die mount area. The top surface of the semiconductor die is provided with a patterned metallization making electrical contact to selected portions of the die. Electrical contact is made between the top surface die metallization and the lead portion of the package by ultrasonically bonded copper ribbon. The die and interconnecting ribbon is then enclosed by an epoxy encapsulant or by a welded metal cover.

Abstract: A solder system for metallurgically bonding a semiconductor die to a metal package member. The solder is based on the tin rich corner of the tin-antimony-silver ternary alloy system. The solder system has particular applicability to the bonding of power transistors.