Patents by Inventor Dennis R. Seguine
Dennis R. Seguine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240283451Abstract: Front-end circuits that combine inductive and capacitive sensing are described. In one embodiment, an apparatus includes a plurality of inductive elements, an inductive measurement circuit, and a frequency divider circuit. The inductive measurement circuit is to output a first signal with a first frequency. The first signal is associated with an inductance change of one of the inductive elements. A feedback circuit can maintain the sinusoidal operation of the first signal. The frequency divider circuit can generate a second signal with a second frequency that is lower than the first frequency.Type: ApplicationFiled: March 18, 2024Publication date: August 22, 2024Applicant: Cypress Semiconductor CorporationInventors: Paul M. Walsh, Kofi MAKINWA, Matheus PIMENTA, Çagri GÜRLEYÜK, Dermot MACSWEENEY, Daniel O'KEEFFE, Dennis R. SEGUINE
-
Patent number: 11552635Abstract: One inductive sensor is configured to maintain a fixed frequency in a resonant circuit. One apparatus includes an inductance-to-digital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.Type: GrantFiled: December 19, 2019Date of Patent: January 10, 2023Assignee: Cypress Semiconductor CorporationInventors: Paul M. Walsh, Dermot MacSweeney, Daniel O'Keeffe, Kofi Makinwa, Matheus Pimenta, Dennis R. Seguine, Ça{hacek over (g)}ri Gürleyük
-
Patent number: 11255890Abstract: One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.Type: GrantFiled: August 13, 2020Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Patent number: 11105851Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: GrantFiled: March 17, 2020Date of Patent: August 31, 2021Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
-
Publication number: 20210096164Abstract: One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.Type: ApplicationFiled: August 13, 2020Publication date: April 1, 2021Applicant: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Publication number: 20200373923Abstract: Maintaining a fixed frequency in a resonant circuit of an inductive sensor circuit is described. In one embodiment, an apparatus includes an inductance-to-digital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.Type: ApplicationFiled: December 19, 2019Publication date: November 26, 2020Applicant: Cypress Semiconductor CorporationInventors: Paul M. Walsh, Dermot MacSweeney, Daniel O'Keeffe, Kofi Makinwa, Matheus Pimenta, Dennis R. Seguine, Çagri Gürleyük
-
Publication number: 20200300910Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
-
Patent number: 10761125Abstract: One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.Type: GrantFiled: January 2, 2018Date of Patent: September 1, 2020Assignee: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Patent number: 10634722Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: May 23, 2019Date of Patent: April 28, 2020Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
-
Patent number: 10345377Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: April 3, 2018Date of Patent: July 9, 2019Assignee: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E. Hastings, Dennis R. Seguine
-
Publication number: 20180292454Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: ApplicationFiled: April 3, 2018Publication date: October 11, 2018Applicant: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
-
Publication number: 20180164358Abstract: One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.Type: ApplicationFiled: January 2, 2018Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Patent number: 9960773Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.Type: GrantFiled: September 19, 2016Date of Patent: May 1, 2018Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Carl Ferdinand Liepold, Onur Ozbek
-
Patent number: 9952282Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: September 21, 2015Date of Patent: April 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
-
Patent number: 9863988Abstract: One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.Type: GrantFiled: October 31, 2016Date of Patent: January 9, 2018Assignee: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Patent number: 9634667Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.Type: GrantFiled: March 26, 2015Date of Patent: April 25, 2017Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Bruce E. Byrkett, Carl Ferdinand Liepold, Hans Van Antwerpen
-
Publication number: 20170085268Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.Type: ApplicationFiled: September 19, 2016Publication date: March 23, 2017Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark Hastings, Amsby D. Richardson, JR., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Carl Ferdinand Liepold, Onur Ozbek
-
Publication number: 20170024078Abstract: A technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a capacitance value of a capacitance sensor within the capacitance sense interface to generate a measured capacitance value. The measured capacitance value is analyzed to determine a baseline capacitance value for the capacitance sensor. The baseline capacitance value may be updated based at least in part upon a weighted moving average of the measured capacitance value. The measured capacitance value may also be analyzed to determine whether the capacitance sensor was activated during a startup phase and to adjust the baseline capacitance value in response to determining that the capacitance sensor was activated during the startup phase.Type: ApplicationFiled: October 3, 2016Publication date: January 26, 2017Inventors: Louis W. Bokma, Andrew C. Page, Dennis R. Seguine
-
Patent number: 9513322Abstract: One embodiment includes an I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.Type: GrantFiled: March 21, 2014Date of Patent: December 6, 2016Assignee: Cypress Semiconductor CorporationInventor: Dennis R. Seguine
-
Patent number: 9494627Abstract: A technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a capacitance value of a capacitance sense element. The measured capacitance value is analyzed to determine a baseline capacitance value for the capacitance sensor. The capacitance sense interface monitors a rate of change of the measured capacitance values and rejects an activation of the capacitance sense element as a non-touch event when the rate of change of the measured capacitance values have a magnitude greater than a threshold level, indicative of a maximum rate of change of a touch event.Type: GrantFiled: August 21, 2012Date of Patent: November 15, 2016Assignee: MONTEREY RESEARCH, LLCInventors: Louis W. Bokma, Andrew C. Page, Dennis R. Seguine