Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing intelligent timing aware metal fill optimization for an IC layout. The disclosed methods enable fill tooling to identify the existing metal tile density and provide timing-aware metal fill insertion to specifically target density requirements and enable effective timing characteristics of signal path nets.

Abstract: A target wire is separated into one set of segments based on effective spaces of crossing wires at one target-wire side, and another set of segments based on effective spaces of crossing wires at another target-wire side. Effective widths of crossing wires at the one and other target-wire sides are accumulated. One effective length factor for crossing wires at the one target-wire side is determined, and another effective length factor for crossing wires at the other target-wire side is determined. One or more capacitance values are ascertained for the one and other target-wire sides with reference to a data structure of capacitance per-unit-length for identified configurations. A total capacitance is determined using the effective length factors, and the ascertained capacitance values. An impact of the determined total capacitance on circuit performance is assessed, and based on the assessing, the wiring pattern of the integrated circuit is modified.

Abstract: Embodiments include translation of an integrated circuit design data into a production file. Aspects of the invention include identifying a top cell in the integrated circuit design data and a first cell-file associated with the top cell, assigning the first cell-file to a first translation module of a plurality of translation modules, and receiving, from the first translation module, an identification of child cells referenced by the first cell-file. Aspects also include assigning cell-files of the integrated circuit design data that correspond to each of the child cells to different translation modules of the plurality of translation modules, receiving, by a merger module, a single-cell production file from each of the plurality of translation modules, wherein each single-cell production file corresponds to a cell in the integrated circuit design data, and combining, by the merger module, the single-cell production files to create the production file.

Abstract: A method for analyzing an area of a target wire includes determining a wiring pattern for performing pattern-based 3D capacitance extraction, determining the target wire included in the wiring pattern, and dividing the target wire into segments based on effective spaces of various crossing wires. The method further includes determining a capacitance analysis that applies for each of the segments, determining a plurality of capacitance results corresponding to the capacitance analysis applied to each of the segments, and accumulating the plurality of capacitance results to extract a total capacitance corresponding to the target wire. The segments are based on an effective spacing of crossing wires, which are located above the target wire and extend across the target wire. The effective spaces are determined using a parameterized function that implements at least two adjustable parameters that are set to obtain the wiring pattern using a fitting process.

Abstract: The invention is a device for sealing a hole or valve in a petroleum tank to prevent emissions, while optionally also automatically greasing a cable in a measured amount to combat friction and a method of use of such device, along with methods of manufacture and use.

Abstract: An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.

Abstract: An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.

Abstract: An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

Abstract: The invention is a device for sealing a hole or valve in a petroleum tank to prevent emissions, while optionally also automatically greasing a cable in a measured amount to combat friction and a method of use of such device, along with methods of manufacture and use.

Abstract: Methods and apparatuses for environmental control systems are described. In one example, a method includes monitoring a voice communications call between a local call participant located in a building space and a remote call participant. The method includes detecting a change in a user state of the local call participant from the voice communications call. The method further includes adjusting an environmental parameter in the building space responsive to detecting the change in the user state of the local call participant.

Abstract: Methods and apparatuses for environmental control systems are described. In one example, a method includes monitoring a voice communications call between a local call participant located in a building space and a remote call participant. The method includes detecting a change in a user state of the local call participant from the voice communications call. The method further includes adjusting an environmental parameter in the building space responsive to detecting the change in the user state of the local call participant.

Abstract: This invention relates to bulk liquid storage tanks, and in particular to an improved tank gauge for measuring the amount of liquid within the tank and for monitoring the movement or settling of the storage tank.

Abstract: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

Abstract: This invention relates to bulk liquid storage tanks, and in particular to an improved tank gauge for measuring the amount of liquid within the tank and for monitoring the movement or settling of the storage tank.

Abstract: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

Abstract: A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.

Abstract: A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.

Abstract: An apparatus for reducing the power consumed by, and the noise generated at the output of a charge pump which is part of a phase locked loop circuit. A reduction in the power consumed by the charge pump is achieved by synchronizing the powering up of the charge pump bias circuit to the state of the counters which control the timing of the signal which triggers a charge pump cycle. In this way current is supplied to the charge pump circuit only when needed for the operation of the pump. A reduction in the noise present at the output of the charge pump caused by the reloading of the counters while the pump is activated is achieved by loading a portion of the counter bits prior to activating the pump. A circuit detects when the counter is close to a value of zero and produces a signal which loads the most significant bits of the counter. When the counter reaches a value of zero, the remaining bits are loaded.

Abstract: An apparatus (10) and method for testing the continuity of two optical fibers (12, 14) nonsimultaneously utilizing a single optical path. Two test light beams from a dual hybrid laser (30) are collimated and directed down a single optical path time-sequentially. The two light beams are linearly polarized in orthogonal planes. A quarter wave plate (42) converts the linearly polarized light into circularly polarized light, and an optical sequencer (22) directs the circularly polarized beams to a plurality of desired optical paths, each path comprising one or two optical fibers (12, 14). A second quarter wave plate (50) converts the circularly polarized light back into linearly polarized light, and a polarizing beamsplitter (24) reflects one of the beams and transmits the other. The two beams then enter the optical fibers (12, 14), where they are reflected by dichroic mirrors (26, 28) at the opposite end of the fibers (12, 14).

Abstract: Apparatus for reading information stored in a track pattern on a radiation reflecting record comprises a source of radiation such as a laser for supplying at least a reading beam, an objective lens assembly for passing the reading beam to the record and for controllably focusing the reading beam at a plane of focus, a photodetector array disposed in an optical path with the lens assembly for sensing at least the recorded information and focusing errors, and an astigmatic element disposed in the optical path for producing an astigmatic image of the reading beam in which the photodetector array comprises a unitary data photodetector disposed for impingement thereon of a zero order reading beam component for sensing the recorded information, and a quadrant photodetector array adjacent to the unitary data photodetector and including separated sectors disposed along orthogonal axes for sensing relative differences of the astigmatic image along the orthogonal axes to provide at least focus error correction signals