Abstract: A device and method for selecting implementations for operators for a neural network which includes a set of different operators of an operator type, for providing a computing device including the neural network. Subsets of the set of different operators are determined. For each subset, a set of implementations for the operators of the relevant subset is determined. For each implementation of the set, at least one metric is determined that characterizes an implementation of the neural network with the implementation on the computing device, in particular a latency, a throughput, or an energy consumption of the implementation of the neural network with the implementation on the computing device. For each set of implementations, one implementation is selected, wherein the implementations are selected that are Pareto-optimal with respect to the at least one metric and a size of an implementation of the neural network with the selected implementations.

Abstract: A computer-implemented method of implementing a computation using a hardware-accelerated instruction of a processor system by solving a constraint satisfaction problem. A solution to the constraint satisfaction problem represents a possible invocation of the hardware-accelerated instruction in the computation. The constraint satisfaction problem assigns nodes of a data flow graph of the computation to nodes of a data flow graph of the instruction. The constraint satisfaction problem comprises constraints enforcing that the assigned nodes of the computation data flow graph have equivalent data flow to the instruction data flow graph, and constraints restricting which nodes of the computation data flow graph can be assigned to the inputs of the hardware-accelerated instruction, with restrictions being imposed by the hardware-accelerated instruction and/or its programming interface.

Abstract: A computer-implemented method to generate instructions for a computing device. A first graph having nodes and edges is provided, which defines first instructions for the computing device. At least one first part is sought in the first graph. A second part is determined as a function of the at least one first part. A directed, acyclic, linked second graph having nodes and edges is determined as a function of the first graph. In the second graph, the first part is replaced by the second part. The second graph defines second instructions for the computing device for executing the computational algorithm. A pattern for at least a part of a graph is provided, whose nodes and edges are defined by instructions that are executable by the computing device. The first graph or the second graph is selected as a function of the pattern, to generate instructions for the computing device.

Abstract: A computer-implemented method of implementing a computation using a hardware-accelerated instruction of a processor system by solving a constraint satisfaction problem. A solution to the constraint satisfaction problem represents a possible invocation of the hardware-accelerated instruction in the computation. The constraint satisfaction problem assigns nodes of a data flow graph of the computation to nodes of a data flow graph of the instruction. The constraint satisfaction problem comprises constraints enforcing that the assigned nodes of the computation data flow graph have equivalent data flow to the instruction data flow graph, and constraints restricting which nodes of the computation data flow graph can be assigned to the inputs of the hardware-accelerated instruction, with restrictions being imposed by the hardware-accelerated instruction and/or its programming interface.