Abstract: A framer-demultiplexer circuit provides means for reducing the high serial bit-stream rate of byte-interleaved low level signal frame structures proposed by the Synchronous Optical Network (SONET) signal hierarchy to speeds which can be processed with low-power low-cost CMOS VLSI technology, while establishing and maintaining basic byte integrity. In this circuitry the incoming high-rate serial bit stream is divided alternately between shift registers 43, 44 under the control of a single high-precision clock-division circuit to provide a multi-bit formatting that enables parallel delivery of stage bytes with the multifold reduction in transmission to a rate within the processing capabilities of CMOs devices.