Abstract: A commuications control system for distributing execution of communication connecting among the service access points of a local multiprocessor computer system and remote computer systems interconnected by a communications network. A load balancing module includes a local user list for storing the number of communications connections being executed by each local access point and a remote user list for storing the number of communication connections between each local service access point in the local computer system and each remote service access point.

Abstract: A communications control system in a multi-processor system includes a connection distribution data structure, including, for each central processing unit, a connection count means for storing a number representing the number of communication connections currently being executed by the corresponding central processing unit, and a gate driver interface service module. The gate driver interface service module is a single task resident in the computer system memory with an active invocation in a single central processing unit of the processing system. The gate driver interface service module responds to each request by selecting the central processing unit presently executing the least number of communication connections, and assigning the communication connection to the central processing unit for execution by constructing a corresponding control block containing the identification of the central processing unit assigned to execute the communication operation.

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. Included among the devices is a communication controller. An interrupt controller processes the device interrupt requests by sending out a vector address to the microprocessor. This enables the microprocessor to branch to a subroutine to process the interrupt. Apparatus is provided to enable the communication controller to generate vector addresses when it sends an interrupt request to the interrupt controller.

Abstract: An apparatus for varying the pulse width of a computer clock by adding a predetermined amount of time to the clock pulse width. A synchronous counter is combined with a latch into a circuit whereby a pulse input to the circuit resets both the latch and counter on the leading edge, and whereby the trailing edge of the input pulse releases the latch and counter allowing the counter to count clock pulses. On a predetermined pulse the counter's carry-output terminal clocks a logic high into the D latch terminal. Concurrently, an output from the latch is fed back to the counter's count-enable input to disable counting until a subsequent pulse resets the circuit. The net effect is to add a predetermined amount of time to the input pulse so that the extended pulse is available at the output of the latch.