Abstract: A computer-implemented method includes executing one or more test programs on a computing device, where the computing device includes a Guarded Storage (GS) facility managing use of GS. Each test program of the one or more test programs comprises a respective GS event, and each respective GS event prompts execution of a respective garbage reclaim function associated with the GS. A memory storage is analyzed, by a computer processor, to verify expected operation of each of the one or more test programs. Test results of the one or more test programs are determined based on the analyzing the memory storage. A remedial action is performed in response to the test results of the one or more test programs.

Abstract: A computer-implemented method includes executing one or more test programs on a computing device, where the computing device includes a Guarded Storage (GS) facility managing use of GS. Each test program of the one or more test programs comprises a respective GS event, and each respective GS event prompts execution of a respective garbage reclaim function associated with the GS. A memory storage is analyzed, by a computer processor, to verify expected operation of each of the one or more test programs. Test results of the one or more test programs are determined based on the analyzing the memory storage. A remedial action is performed in response to the test results of the one or more test programs.

Abstract: A computer-implemented method for testing a hybrid architecture instruction set is provided. The method includes defining a first instruction definition table for a first base architecture, and defining a second instruction definition table for a second base architecture, wherein the first base architecture is different than the second base architecture. The method also includes defining a delta table, wherein the delta table defines architecture specific behavior, and generating a hybrid architecture table based on the delta table and at least one of the first instruction definition table or the second instruction definition table. The method includes executing a test based on the hybrid architecture table, wherein the hybrid architecture table is for a hybrid architecture that is compatible between the first base architecture and the second base architecture.

Abstract: An aspect includes include selective purging of entries from translation look-aside buffers (TLBs). A method includes building multiple logical systems in a computing environment, the multiple logical systems including at least two level-two guests. TLB entries are created in a TLB for the level-two guests by executing fetch and store instructions. A subset of the TLB entries is purged in response to a selective TLB purge instruction, the subset including TLB entries created for a first one of the level-two guests. Subsequent to the purging, verifying that the subset of the TLB entries were purged from the TLB, and determining whether a second one of the level-two guests is operational, the determining including executing at least one instruction that accesses a TLB entry of the second one of the level-two guests. Test results are generated based on the verifying and the determining. The test results are output.

Abstract: A computer-implemented method for testing a hybrid architecture instruction set is provided. The method includes defining a first instruction definition table for a first base architecture, and defining a second instruction definition table for a second base architecture, wherein the first base architecture is different than the second base architecture. The method also includes defining a delta table, wherein the delta table defines architecture specific behavior, and generating a hybrid architecture table based on the delta table and at least one of the first instruction definition table or the second instruction definition table. The method includes executing a test based on the hybrid architecture table, wherein the hybrid architecture table is for a hybrid architecture that is compatible between the first base architecture and the second base architecture.

Abstract: An aspect includes receiving a symbol translation table (STT) that includes input symbols and their corresponding codewords. An entropy encoding descriptor (EED) that specifies how many of the codewords have each of the different lengths is also received. Contents of one or both of the STT and the EED are modified to generate a test case and an entropy encoding test is executed. The executing includes performing a lossless data compression process based on contents of an input data string that includes one or more of the input symbols, and on contents of the STT and the EED; or performing a data expansion process based on contents of an input data string that includes one or more of the codewords, and on contents of the STT and the EED. A result of the entropy encoding test is compared to an expected result.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution, testing, by the computing device, the transaction execution in a uni-processing system based on the instruction stream, and outputting, by the computing device, a status of the test to one or more output devices. A determination may be made that an abort occurs in the transaction execution based on the testing.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution, testing, by the computing device, the transaction execution in a uni-processing system based on the instruction stream, and outputting, by the computing device, a status of the test to one or more output devices. A determination may be made that an abort occurs in the transaction execution based on the testing.

Abstract: A system for testing a base machine includes the base machine that has a base feature set (BFS) and a testing module. The system also includes a test case generator, configured to: select a prior level of the base machine, the prior level having a legacy architecture; determine a feature set of the legacy architecture based on the BFS; generate a set of test instructions based on the feature set; and provide the set of test instructions to the testing module.

Abstract: A system for testing a base machine includes the base machine that has a base feature set (BFS) and a testing module. The system also includes a test case generator, configured to: select a prior level of the base machine, the prior level having a legacy architecture; determine a feature set of the legacy architecture based on the BFS; generate a set of test instructions based on the feature set; and provide the set of test instructions to the testing module.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A method, system, and computer program product for generating terminating, pseudo-random test instruction streams, including forward and backward branching instructions. A first instruction stream is generated, including at least one backward branching instruction and at least one forward branching instruction. Each backward branching instruction is preceded by at least one forward branching instruction, which is used to guarantee termination of the loop formed by the backward branching instruction. Backward branching targets are resolved when the backward branching instruction is inserted into the first instruction stream. Forward branching targets remain unresolved in the first instruction stream. A set of potential branch targets is determined for each forward branching instruction. For each forward branching instruction, a branch target is randomly selected from the set of potential branch targets for that forward branching instruction.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.