Abstract: A testing facility is provided to test the multithreading functionality of a computing environment. The testing of this functionality includes building independent instruction streams to test threads of a multi-threaded environment while honoring architecturally imposed common fields and constraints, if any, of the threads. Certain features may be enabled/disabled for all threads. The instruction streams generated for testing this functionality may vary from being identical for all the threads being tested to being totally different, such as having different architectures.

Abstract: Compare points are detected in a multi-threaded computing environment. One thread of the multi-threaded computing environment has reached a compare point for the one thread. The compare point for the one thread being a point at which results of executing a test case on the one thread is ready to be compared against expected results for that test case. A determination is made as to whether another thread of the multi-threaded computing environment has reached a compare point for the another thread. Execution of the another thread is continued, based on determining the another thread has not reached the compare point for the another thread. The test case of the one thread is, however, not re-executed.

Abstract: A computer program product is provided for performing a method including: generating a test instruction stream of a program that includes a plurality of executable instructions; setting controls for a runtime-instrumentation process; simulating execution of the test instruction stream and sampling of the test instruction stream according to the controls, and storing simulated records associated with the sampling in a predicted collection buffer (PCB); accessing a program buffer of a processor, the program buffer storing records associated with sampling the test instruction stream according to the controls during execution of the test instruction stream by the processor; examining individual records in the program buffer to determine whether the individual records are valid and in proper sequence; and comparing the simulated records of the PCB and the records of the program buffer to validate the program buffer.

Abstract: A computer program product is provided for performing a method including: generating a test instruction stream of a program that includes a plurality of executable instructions; setting controls for a runtime-instrumentation process; simulating execution of the test instruction stream and sampling of the test instruction stream according to the controls, and storing simulated records associated with the sampling in a predicted collection buffer (PCB); accessing a program buffer of a processor, the program buffer storing records associated with sampling the test instruction stream according to the controls during execution of the test instruction stream by the processor; examining individual records in the program buffer to determine whether the individual records are valid and in proper sequence; and comparing the simulated records of the PCB and the records of the program buffer to validate the program buffer.

Abstract: A method, system, and computer program product for generating terminating, pseudo-random test instruction streams, including forward and backward branching instructions. A first instruction stream is generated, including at least one backward branching instruction and at least one forward branching instruction. Each backward branching instruction is preceded by at least one forward branching instruction, which is used to guarantee termination of the loop formed by the backward branching instruction. Backward branching targets are resolved when the backward branching instruction is inserted into the first instruction stream. Forward branching targets remain unresolved in the first instruction stream. A set of potential branch targets is determined for each forward branching instruction. For each forward branching instruction, a branch target is randomly selected from the set of potential branch targets for that forward branching instruction.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.