Patents by Inventor Dennis Yost

Dennis Yost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130138632
    Abstract: Systems and methods of aircraft trending are described. In one example, a method of aircraft trend analysis includes receiving, at a computing device, data from a plurality of aircraft in a fleet of aircraft. The data includes system level data for each of the plurality of aircraft. The received data is stored in a database. The computing device analyzes the stored data to identify fleet trends and generates one or more trend analysis reports for the fleet based at least in part on the fleet trends.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Inventor: Dennis Yost
  • Patent number: 7718009
    Abstract: Cleaning solutions and cleaning methods targeted to particular substrates and structures in semiconductor fabrication are described. A method of cleaning fragile structures having a dimension less than 0.15 um with a cleaning solution formed of a solvent having a surface tension less than water while applying acoustic energy to the substrate on which the structures are formed is described. Also, a method of cleaning copper with several different cleaning solutions, and in particular an aqueous sulfuric acid and HF cleaning solution, is described. Also, methods of cleaning both sides of a substrate at the same time with different cleaning solutions applied to the top and the bottom are described.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: May 18, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Steven Verhaverbeke, Jianshe Tang, Roman Gouk, Brian J. Brown, Han-Wen Chen, Ching-Hwa Weng, James S. Papanu, Dennis Yost
  • Patent number: 7521374
    Abstract: According to one aspect of the present invention, a method and apparatus for cleaning a semiconductor substrate is provided. The method may include supporting a semiconductor substrate, the semiconductor substrate having a surface, and dispensing an amount of semiconductor substrate processing liquid onto the surface of the semiconductor substrate, the amount of semiconductor substrate processing liquid being such that substantially none of the semiconductor substrate processing liquid flows off the surface of the semiconductor substrate. The semiconductor substrate processing fluid may form a standing puddle on the surface of the semiconductor substrate. The semiconductor substrate may be rotated while the semiconductor substrate processing liquid is on the surface of the semiconductor substrate such that substantially all of the amount of semiconductor substrate processing liquid remains on the surface of the semiconductor substrate during said rotation.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: April 21, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Steven Verhaverbeke, Dennis Yost, Roman Gouk
  • Publication number: 20080059261
    Abstract: A method for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.
    Type: Application
    Filed: November 5, 2007
    Publication date: March 6, 2008
    Inventors: John Madok, Dennis Yost, Bobin Cheung
  • Publication number: 20080041427
    Abstract: Embodiments of the invention provide methods of applying a liquid to a backside of a substrate to bring the substrate to the temperature of the liquid. By controlling the temperature of the substrate the temperature of the semiconductor processing liquid may be maintained at a particular temperature or a type of reaction occurring in the semiconductor processing liquid may be enhanced or maintained, such as in reactions where relatively small amounts of liquid are used or expensive chemicals are used.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 21, 2008
    Inventors: Brian Brown, Dennis Yost, James Papanu, Jianshe Tang, Alexander Ko
  • Patent number: 7227244
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: June 5, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20070082477
    Abstract: The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via hole is partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the via hole. A substantially conformal sacrificial layer is deposited on the top surface of the dielectric stack and in the recess. Then, a photoresist layer is deposited on the sacrificial fill. A trench etch mask overlaying the via hole, is developed in the photoresist layer. This mask is etched through the sacrificial layer that is formed on the top surface of the dielectric stack as well as through the sacrificial fill and sacrificial layer that is present in the via hole.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 12, 2007
    Inventors: Mehul Naik, Srinivas Gandikota, Girish Dixit, Dennis Yost
  • Publication number: 20060254616
    Abstract: Embodiments of the invention provide methods of applying a liquid to a backside of a substrate to bring the substrate to the temperature of the liquid. By controlling the temperature of the substrate the temperature of the semiconductor processing liquid may be maintained at a particular temperature or a type of reaction occurring in the semiconductor processing liquid may be enhanced or maintained, such as in reactions where relatively small amounts of liquid are used or expensive chemicals are used.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Inventors: Brian Brown, Dennis Yost, James Papanu, Jianshe Tang, Alexander Ko
  • Publication number: 20060107970
    Abstract: According to one aspect of the present invention, a method and apparatus for cleaning a semiconductor substrate is provided. The method may include supporting a semiconductor substrate, the semiconductor substrate having a surface, and dispensing an amount of semiconductor substrate processing liquid onto the surface of the semiconductor substrate, the amount of semiconductor substrate processing liquid being such that substantially none of the semiconductor substrate processing liquid flows off the surface of the semiconductor substrate. The semiconductor substrate processing fluid may form a standing puddle on the surface of the semiconductor substrate. The semiconductor substrate may be rotated while the semiconductor substrate processing liquid is on the surface of the semiconductor substrate such that substantially all of the amount of semiconductor substrate processing liquid remains on the surface of the semiconductor substrate during said rotation.
    Type: Application
    Filed: November 23, 2004
    Publication date: May 25, 2006
    Inventors: Steven Verhaverbeke, Dennis Yost, Roman Gouk
  • Publication number: 20060088949
    Abstract: The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 27, 2006
    Inventors: Michael Smayling, Dennis Yost
  • Publication number: 20060042651
    Abstract: Cleaning solutions and cleaning methods targeted to particular substrates and structures in semiconductor fabrication are described. A method of cleaning fragile structures having a dimension less than 0.15 um with a cleaning solution formed of a solvent having a surface tension less than water while applying acoustic energy to the substrate on which the structures are formed is described. Also, a method of cleaning copper with several different cleaning solutions, and in particular an aqueous sulfuric acid and HF cleaning solution, is described. Also, methods of cleaning both sides of a substrate at the same time with different cleaning solutions applied to the top and the bottom are described.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Inventors: Steven Verhaverbeke, Jianshe Tang, Roman Gouk, Brian Brown, Han-Wen Chen, Ching-Hwa Weng, James Papanu, Dennis Yost
  • Publication number: 20050084206
    Abstract: A fiberoptic wavelength combiner comprises: a collimating lens having a first surface and a second surface, opposite the first surface; two input optical fibers secured to the first surface, each input optical fiber conducting light at a wavelength that is different from other input optical fibers; a wedged mirror spaced from the second surface, the wedged mirror having a front surface facing the collimating lens and a rear surface, the front surface provided with a first reflective coating and the rear surface provided with a second reflective coating; and an output optical fiber secured to the first surface, whereby light from the input optical fibers is collimated by the lens and made incident on the wedged mirror and its first and second reflective coatings to thereby direct the light back through the collimating lens onto the output optical fiber. Further, a method of aligning the fiberoptic wavelength combiner is provided.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Inventors: Mikhail Gutin, Boyd Hunter, Dennis Yost
  • Patent number: 6858153
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: February 22, 2005
    Assignee: Applied Materials Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20050023694
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Application
    Filed: August 24, 2004
    Publication date: February 3, 2005
    Inventors: Claes Bjorkman, Melissa Yu, Hongqing Shan, David Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Chapra, Gerald Yin, Farhad Moghadam, Judy Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Patent number: 6669858
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: December 30, 2003
    Assignee: Applied Materials Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20020084257
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Application
    Filed: November 5, 2001
    Publication date: July 4, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20020074309
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Application
    Filed: November 5, 2001
    Publication date: June 20, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Patent number: 6340435
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: January 22, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim