Abstract: A network interface circuit (NIC) is provided with logic for maintaining various control pointers and at least one control counter for controlling burst transferring of buffered ATM cells to its host computer system in a non-cellboundary-aligned block manner, distinguishing the ATM packet header from the ATM data most of the time, except for a number of predetermined exceptions. More specifically, ATM packet headers and ATM data are to be burst transferred to separate header and data buffers on the host computer system, except for short and atypical packets, in fixed size blocks, where the block size is complementary to the interface bus, but not necessarily aligned with the ATM cell boundaries. For the short and atypical packets, both the header and data are to be burst transferred into the header buffer instead.

Abstract: The asynchronous transfer mode (ATM) interface, which may be a segmentation and reassembly unit, controls segmentation of packets into cells and reassembly of cells into packets for interconnecting a computer system to an ATM system. An architecture is disclosed which partitions load and unload functions within the ATM interface. The load and unload functions are separately partitioned for segmentation and for reassembly. For segmentation, a transmit load engine controls storage of data from packets into an external buffer memory; whereas transmit unload engine handles extracting data from the memory, segmenting the data into cells, and transmitting the cells to the ATM system. For reassembly, a receive load engine handles receiving and storing the cells corresponding to the packets into a memory; whereas a receive unload engine controls extraction of the data from the memory and transmission of the packets to the computer system.