Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each processor unit (PU), which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of processor units couplable to receive data from the memory, and control means for controlling transmission of data from the control means to each processor unit. The control means for controlling operations of the data processor units is arranged to transmit data intended for each processor unit (i.e. broadcast data) to the memory, and is adapted to control each processor unit to receive the broadcast data from the memory. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of processor units couplable to receive data from the memory, and control means for controlling transmission of data from the control means to each processor unit. The control means for controlling operations of the data processor units is arranged to transmit data intended for each processor unit (i.e. broadcast data) to the memory, and is adapted to control each processor unit to receive the broadcast data from the memory. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.

Abstract: An apparatus and method are provided for producing an assembly comprising a memory, a plurality of data buses and an interface for controlling access to the memory by each data bus. The interface is arranged to control memory access so that the plurality of devices can access different parts of the memory substantially simultaneously. A single interface is used to control memory accesses to different parts or elements of a memory substantially simultaneously so that a plurality of, or multiple memory accesses can be performed at the same time.

Abstract: A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.

Abstract: A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.