Patents by Inventor Deog-Ja Koo

Deog-Ja Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538696
    Abstract: A chamber apparatus comprises a lower and an upper chamber body, and a gasket member. The lower chamber body defines a receiving region and a first receiving groove. The upper chamber body disposed above the lower chamber body and defines a second receiving groove projectively align to the first receiving groove. The second receiving groove is configured to establish sealing coupling with the lower chamber body so as to form a chamber enclosure region. The gasket member includes a conductive member and an elastomeric member. The conductive member configured to laterally surround the receiving region and respectively fit into the lower chamber body and the upper chamber body. The elastomeric member is protruded from the conductive member and extended toward the receiving region, configured to be compressed by the upper and the lower chamber body so as to seal the chamber enclosure region.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 27, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Deog-Ja Koo, Dea-Jin Kim
  • Patent number: 11328893
    Abstract: A plasma processing system has been disclosed. The plasma processing system includes an electrostatic chuck (ESC) and an edge ring assembly. The edge ring assembly has a conductive ring configured to generate an electric field to adjust the direction of ions.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 10, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventor: Deog-Ja Koo
  • Publication number: 20210125844
    Abstract: A chamber apparatus comprises a lower and an upper chamber body, and a gasket member. The lower chamber body defines a receiving region and a first receiving groove. The upper chamber body disposed above the lower chamber body and defines a second receiving groove projectively align to the first receiving groove. The second receiving groove is configured to establish sealing coupling with the lower chamber body so as to form a chamber enclosure region. The gasket member includes a conductive member and an elastomeric member. The conductive member configured to laterally surround the receiving region and respectively fit into the lower chamber body and the upper chamber body. The elastomeric member is protruded from the conductive member and extended toward the receiving region, configured to be compressed by the upper and the lower chamber body so as to seal the chamber enclosure region.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Inventors: DEOG-JA KOO, DEA-JIN KIM
  • Publication number: 20200203115
    Abstract: A plasma processing system has been disclosed. The plasma processing system includes an electrostatic chuck (ESC) and an edge ring assembly. The edge ring assembly has a conductive ring configured to generate an electric field to adjust the direction of ions.
    Type: Application
    Filed: October 25, 2019
    Publication date: June 25, 2020
    Inventor: DEOG-JA KOO
  • Patent number: 9412610
    Abstract: A method of manufacturing a semiconductor device is disclosed. In the method, a substrate having a first surface and a second surface is provided. The second surface is opposed to the first surface. A via hole is formed to penetrate the substrate from the first surface toward the second surface. The via hole includes a first portion and a second portion. The first portion has a first sidewall which is substantially perpendicular to the first surface. The second portion has a second sidewall which gradually decreases from the first surface toward the second surface, and has a bottom surface that substantially flat. A seed pattern is formed on the first sidewall of the first portion, the second sidewall of the second portion and the bottom surface of the second portion of the via hole. A first thickness (Vt) of the seed pattern on the first sidewall of the first portion is less than a second thickness (VIt) of the seed pattern on the second sidewall of the second portion.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hoon Park, Deog-Ja Koo, Gyung-Jin Min
  • Publication number: 20150255301
    Abstract: A method of manufacturing a semiconductor device is disclosed. In the method, a substrate having a first surface and a second surface is provided. The second surface is opposed to the first surface. A via hole is formed to penetrate the substrate from the first surface toward the second surface. The via hole includes a first portion and a second portion. The first portion has a first sidewall which is substantially perpendicular to the first surface. The second portion has a second sidewall which gradually decreases from the first surface toward the second surface, and has a bottom surface that substantially flat. A seed pattern is formed on the first sidewall of the first portion, the second sidewall of the second portion and the bottom surface of the second portion of the via hole. A first thickness (Vt) of the seed pattern on the first sidewall of the first portion is less than a second thickness (VIt) of the seed pattern on the second sidewall of the second portion.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventors: Seung-Hoon Park, Deog-Ja Koo, Gyung-Jin Min