Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

Abstract: A memory system includes a semiconductor memory device and a test device. The semiconductor memory device includes a memory cell array, an error correction circuit and a test circuit. The test device controls a test of the semiconductor memory device, and the test device includes a first fail address memory and a second fail address memory. The test circuit performs a first test on the memory cell array to selectively record a first test result associated with the first test in the first fail address memory and performs a second test on the memory cell array to record a second test result associated with the second test in the second fail address memory. The test circuit is configured to perform the first test and the second test based on a test pattern data from the test device in a test mode.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

Abstract: A fault distribution generation system is provided. The fault distribution generation system comprises: a fail address mapping module which receives a fail bit map representing failures included in a semiconductor device as a plurality of pixels having a plurality of different failure levels and fail addresses for the failures included in the semiconductor device, and maps the fail addresses to each pixel of the fail bit map; a fault pattern analyzing module which receives information on each pixel to which the fail addresses are mapped from the fail address mapping module, analyzes the received information, and classifies the failures included in each pixel into predetermined fault patterns; and a fault distribution estimating module which estimates an occurrence probability distribution of the fault patterns according to the failure levels based on results of the classification of the fault pattern analyzing module.