Patents by Inventor Deok-sung Hwang

Deok-sung Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083384
    Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 14, 2024
    Applicants: Hyundai Motor Company, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.
    Inventors: Sang Soo LEE, Chan Ho JUNG, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Deok Soo LIM, Sang Do PARK, In Sun BAEK, Sin Chan YANG, Chan Ki CHO, Myung Soo LEE, Jae Yong JANG, Jun Sik HWANG, Ho Sung KANG, Hae Dong KWAK, Hyun Tak KO
  • Patent number: 8791526
    Abstract: A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Hyeong-sun Hong, Kwang-youl Chun, Makoto Yoshida, Deok-sung Hwang, Chul Lee
  • Patent number: 8502341
    Abstract: Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Lee, Hyeong-Sun Hong, Deok-Sung Hwang, Jae-Man Yoon, Bong-Soo Kim
  • Publication number: 20120214297
    Abstract: A method of fabricating a semiconductor device includes partially removing an active region and an isolation region to form a gate buried trench, forming a gate insulating layer on an inner wall of the gate buried trench, forming a gate conductive pattern on the gate insulating layer to fill the gate buried trench, and a height of an uppermost surface of the gate conductive pattern is lower than a height of an uppermost surface of the substrate. The method also includes forming an interlayer insulating layer on the substrate and on the gate conductive pattern, the interlayer insulating layer includes an upper insulating region and a lower insulating region, the lower insulating region fills the gate buried trench, the upper insulating region is formed over the substrate, and forming a bit contact plug connected to the active region through the interlayer.
    Type: Application
    Filed: January 17, 2012
    Publication date: August 23, 2012
    Inventors: Kwan-Sik Cho, Deok-Sung Hwang, Kye-Hee Yeom
  • Publication number: 20120139021
    Abstract: A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hyun Kim, Deok-Sung Hwang, Yun-Jae Lee, Chul Lee, Yoon-Taek Jang, Chang-Hoon Jeon, Sang-Bin Ahn, Jun-Hyeok Ahn
  • Publication number: 20110210421
    Abstract: Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
    Type: Application
    Filed: February 4, 2011
    Publication date: September 1, 2011
    Inventors: CHUL LEE, Hyeong-Sun Hong, Deok-Sung Hwang, Jae-Man Yoon, Bong-Soo Kim
  • Publication number: 20110095350
    Abstract: A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
    Type: Application
    Filed: September 28, 2010
    Publication date: April 28, 2011
    Inventors: Jae-man Yoon, Hyeong-sun Hong, Kwang-youl Chun, Makoto Yoshida, Deok-sung Hwang, Chul Lee