Patents by Inventor Deqin Yu

Deqin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional memory structure and manufacturing method thereof
    Patent number: 10756102
    Abstract: A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Deqin Yu, Wenbin Zhou, Yong Hui Gao
  • THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190157287
    Abstract: A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.
    Type: Application
    Filed: October 2, 2018
    Publication date: May 23, 2019
    Inventors: ZONGLIANG HUO, Deqin Yu, Wenbin Zhou, Yong Hui Gao