Patents by Inventor Der-Chyang Yeh

Der-Chyang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9373527
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung
  • Publication number: 20160163566
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Application
    Filed: June 18, 2015
    Publication date: June 9, 2016
    Inventors: Hsien-Wei Chen, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen
  • Publication number: 20160155730
    Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.
    Type: Application
    Filed: March 27, 2015
    Publication date: June 2, 2016
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Shih-Peng Tai
  • Publication number: 20160118301
    Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
    Type: Application
    Filed: January 8, 2016
    Publication date: April 28, 2016
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 9324698
    Abstract: A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer. The device further comprises a redistribution layer formed on a top surface of a first side of the encapsulation layer, wherein the redistribution layer is connected to active circuits of the first chip and the second chip and the redistribution layer extends beyond at least one edge of the first chip and the second chip.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 9305864
    Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
  • Publication number: 20160079171
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Der-Chyang Yeh, Hsien-Wei Chen, Ming-Yen Chiu, Ying-Ju Chen
  • Publication number: 20160079190
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.
    Type: Application
    Filed: January 26, 2015
    Publication date: March 17, 2016
    Inventors: Chen-Hua Yu, Chien-Yu Li, Hung-Jui Kuo, Li-Hsien Huang, Hsien-Wei Chen, Der-Chyang Yeh, Chung-Shi Liu, Shin-Puu Jeng
  • Publication number: 20160071829
    Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).
    Type: Application
    Filed: November 26, 2014
    Publication date: March 10, 2016
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, An-Jhih Su
  • Publication number: 20160071820
    Abstract: Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 10, 2016
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen
  • Patent number: 9275923
    Abstract: Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou, Shuo-Mao Chen, Der-Chyang Yeh
  • Patent number: 9275950
    Abstract: An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou, Der-Chyang Yeh, Chuei-Tang Wang
  • Patent number: 9263511
    Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh
  • Publication number: 20160013138
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 14, 2016
    Inventors: Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu, Chien-Fu Tseng
  • Publication number: 20160005716
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Publication number: 20150380388
    Abstract: A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. One of the device die and the plurality of dies includes a semiconductor substrate and a through-via penetrating through the semiconductor substrate, A polymer region includes portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first and the second plurality of metal pillars. Redistribution lines are formed over the first and the second plurality of metal pillars.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Publication number: 20150357319
    Abstract: Exemplary methods of forming the semiconductor device, encompasses forming a first package with at least one first die on a packaging substrate that is removably coupled to a carrier. Forming a thermal contact pad on the first die package, with or without a surrounding seal ring, and bonding a second die package to the first die package where the thermal contact pad is between the two packages. Electrically coupling the first die package to the second die package with a set of conductive elements and removing the carrier from the first package.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Chen-Hua YU, Der-Chyang YEH
  • Publication number: 20150348904
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 3, 2015
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 9196586
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Yen Chiu, Der-Chyang Yeh
  • Publication number: 20150294939
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su