Abstract: A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip.

Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<?<90°. The heat spreader is disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate. The adhesive layer is surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening.

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Abstract: A structure includes a bridge die. The bridge die includes a semiconductor substrate; and an interconnect structure over the semiconductor substrate. The interconnect structure includes dielectric layers and conductive lines in the dielectric layers, an encapsulant encapsulating the bridge die therein, and a redistribution structure over the bridge die. The redistribution structure includes redistribution lines therein. A first package component and a second package component are bonded to the redistribution lines. The first package component and the second package component are electrically interconnected through the redistribution lines and the bridge die.

Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.

Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.

Abstract: A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.

Abstract: A semiconductor device and the manufacturing method thereof are provided. The semiconductor device includes a package structure, a first die, a first containment structure, a pre-fill layer, and a plurality of conductive terminals. The package structure includes an attach zone, a keep-out zone around the attach zone. The first die is disposed on the package structure in the attach zone and electrically connected to the package structure. The first containment structure is disposed within the keep-out zone of the package structure and surrounds the first die. The pre-fill layer is disposed between the package structure and the first die and between the first containment structure and the first die, where the pre-fill layer is constrained within the first containment structure. The conductive terminals are disposed on the package structure, distributed around the keep-out zone of the package structure, and electrically connected to the package structure.

Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.