Abstract: A semiconductor structure includes a substrate and a contact field plate (CFP) on the substrate. The contact field plate includes an insulation layer on the substrate, a poly gate over the insulation layer, a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.

Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.

Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.

Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.

Abstract: A method for fabricating a hollow nanotube structure is disclosed. The method includes the steps of providing a substrate, developing a plurality of nanowires on the substrate with a predetermined size on the seed layer at relatively low temperature by a hydro-thermal growth method, forming an outer covering layer on the surfaces of the nanowires, selectively etching an upper end of the outer coating layer to expose an upper end of the nanowires and removing the nanowires to remain the hollow outer coating layer to form a plurality of hollow nanotubes. The method can simplify the nanotube manufacturing process, increase the dimension precision of the nanotubes and enhance the photoelectric properties of micro-electro-mechanical elements.