Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.

Abstract: A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.

Abstract: A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.

Abstract: This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.

Abstract: A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.

Abstract: A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: A non-volatile memory unit includes a substrate on which a source diffusion region and a drain diffusion region are formed. A first dielectric layer and a tunnel dielectric layer are formed between the source diffusion region and the drain diffusion region, are respectively on the drain diffusion region side and the source diffusion region side, and are connected to each other. A select gate is formed on the first dielectric layer. A source insulating layer is formed on the source diffusion region. The tunnel dielectric layer extends to the source diffusion region and is connected to the source insulating layer. A floating gate is formed on a face of the tunnel dielectric layer and a face of the thicker source insulating layer. A control gate is formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.