Patents by Inventor Der Yi Sheu

Der Yi Sheu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7170116
    Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: January 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher K. Y. Chun, Der Yi Sheu
  • Patent number: 6927429
    Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 9, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher K. Y. Chun, Der Yi Sheu
  • Publication number: 20040159858
    Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: Christopher K.Y. Chun, Der Yi Sheu