Abstract: A gray-scale method for a flat panel display is provided, which includes the following: A plurality of scan-line initial signals are provided during a frame period. The scan-line initial signals are transmitted sequentially. According to the scan-line initial signals, the scan-lines are scanned. In which, the frame period includes X horizontal periods. And each horizontal period includes Y initial periods. X and Y each is a positive integer. The scan-line initial signal Kij is appeared during the jth initial period of the ith horizontal period. In which, the i and j at one to one correspondence. The i and j each is a positive integer where 1?i?X and 1?j?Y.

Abstract: A low-power-consumption source driver for a liquid crystal display is provided. More than one middle voltage level for the level shifter and the output buffer is provided, in addition to the power supply voltage level VDD and the ground level GND, to provide different voltage levels for image data of different polarities. Hence, amplitude of the operational voltage of the level shifters and the analog circuits with different polarities can be reduced. It also can reduce the amplitude of the operational voltage of the level shifter and can reduce significantly the dynamic power consumption of the level shifter and the DAC. Because the voltage amplitude of the circuit is reduced and a low-voltage tolerated device can be used, so that the present invention can further reduce the cost of the circuit.

Abstract: A driving method and data driving circuit of display is provided. A frame is divided into a first field and a second field, and respectively driving a first and a second part of those data lines within the first and second field. Sequentially driving a first part of the data lines corresponding to the first field and driving a second part of the data lines corresponding to the second field. While said data lines are driving, every two adjacent pixels are respectively applied with a first common voltage with a first polarity and applied with a second common voltage with a second polarity within a time period of the frame, where the first polarity is opposite to the second polarity, and the first part and the second part of the data lines are interlaced arrangement.

Abstract: A gray-scale method for a flat panel display is provided, which includes the following: A plurality of scan-line initial signals are provided during a frame period. The scan-line initial signals are transmitted sequentially. According to the scan-line initial signals, the scan-lines are scanned. In which, the frame period includes X horizontal periods. And each horizontal period includes Y initial periods. X and Y each is a positive integer. The scan-line initial signal Kij is appeared during the jth initial period of the ith horizontal period. In which, the i and j at one to one correspondence. The i and j each is a positive integer where 1?i?X and 1?j?Y.

Abstract: A liquid crystal display having an apparatus for compensating gray-level luminance is provided. When an N-line inversion driving method is used for a liquid crystal display, the gray-level voltage of the first horizontal line with the same polarity is compensated. N gamma voltages are generated for the mth gray level and a multiplexer is used to select and output a proper voltage to the digital/analog converter. The multiplexer is controlled by a control signal. In positive polarity, the polarity control signal outputs a higher voltage during the period of the first horizontal line inversion. In negative polarity, the polarity control signal outputs a lower voltage during the period of the first horizontal line inversion.

Abstract: A low-power-consumption source driver for a liquid crystal display is provided. Morethan one middle voltage level for the level shifter and the output buffer is provided, in addition to the power supply voltage level VDD and the ground level GND, to provide different voltage levels for image data of different polarities. Hence, amplitude of the operational voltage of the level shifters and the analog circuits with different polarities can be reduced. It also can reduce the amplitude of the operational voltage of the level shifter and can reduce significantly the dynamic power consumption of the level shifter and the DAC. Because the voltage amplitude of the circuit is reduced and a low-voltage tolerated device can be used, so that the present invention can further reduce the cost of the circuit.