Abstract: A power saving improvement in an injection locked oscillator (ILO) used is described. The ILO circuitry comprises a feedback path to provide a finecal (M-bit fine calibration signal). The feedback path need not be active at all times; only when an event occurs that requires the feedback path to update the value of the finecal signal. A monitor is provided to sense the occurrence of such event which may be, for examples, an end of a time period or a predetermined change in temperature. When the event occurs, the feedback path is activated to update the value of the finecal signal.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Abstract: Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.