Abstract: In some examples, a lock manager may receive a lock release message from a processor. The lock release message may identify a lock that synchronizes control of a shared resource. The lock manager may determine, for the lock identified in the lock release message, multiple processors contending to acquire the lock and select a particular processor among the multiple processors to acquire the lock.

Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.

Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.

Abstract: According to an example, cache operations may be managed by detecting that a cacheline in a cache is being dirtied, determining a current epoch number, in which the current epoch number is associated with a store operation and wherein the epoch number is incremented each time a thread of execution completes a flush-barrier checkpoint, and inserting an association of the cacheline to the current epoch number into a field of the cacheline that is being dirtied.

Abstract: A method may include receiving a first transaction request. The method may further include transmitting a retry response to the transaction request, which includes a first epoch identifier associated with a current epoch. The method may further include receiving a second transaction request, which includes a second epoch identifier associated with a previous epoch. The second transaction request may be fulfilled using a transaction resource reserved for the previous epoch.

Abstract: A system comprises a processor, a memory fabric, and a fabric bridge coupled to the memory fabric and the processor. The fabric bridge may receive, from the processor a first eviction request comprising first eviction data, transmit, to the processor, a message indicating the fabric bridge has accepted the first eviction request, transmit a first write comprising the first eviction data to the fabric, receive, from the processor, a second eviction request comprising second eviction data, and transmit a second write comprising the second eviction data to the fabric. Responsive to transmitting the second write request, the fabric bridge may transmit, to the processor, a message indicating the fabric bridge accepted the second eviction request, determine that the first write and the second write have persisted, and transmit, to the processor, a notification to the processor responsive to determining that the first write and the second write have persisted.

Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.

Abstract: An apparatus for assisting a flush of a cache is described herein. The apparatus comprises processing element. The processing element is to probe a cache line at an offset address and write the cache line at the offset address to a non-volatile memory in response to a flush instruction at a first address.

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

Abstract: A fabric back pressure timeout transmitting device may include an arbiter, a first queue to supply packets to the arbiter and a second queue to supply packets to the arbiter, a first timer tracking time since transmission of a packet from the first queue with at least one packet in the first queue and a second timer tracking time since transmission of a packet from the second queue with at least one packet in the second queue. The first queue is designated to receive those packets that have a first number of remaining to destination hops. The second queue is designated to receive those packets that have a second number of remaining destination hops different than the first number.

Abstract: A completion packet may be returned before a data packet is written to a memory, if a field of the data packet indicates the data packet was sent due to a cache capacity eviction. The completion packet is returned after the data packet is written to the memory, if the field indicates the data packet was sent due to a flush operation.

Abstract: A blockage is detected at a first link based on a delay and/or stoppage of transmission of a data message along the first link between first and second nodes of a plurality of nodes of a fabric. A snapshot message is sent along at least a second link between the first and second nodes in response to the blockage being detected. The second node may capture a fabric state at the second node in response to receiving the snapshot message, before a corrective action occurs.

Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.

Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.

Abstract: According to an example, a retransmission sequence involving non-idempotent primitives in a fault-tolerant memory fabric may be modified. For example, a redundancy controller may request a sequence to access a stripe in the fault-tolerant memory fabric, wherein the sequence involves a non-idempotent primitive. In response to determining an expiration of a time threshold for the non-idempotent primitive, the redundancy controller may read other data in other cachelines in the stripe, calculate a new parity value by performing an idempotent exclusive-or primitive on the new data with the other data in the stripe, and write the new parity to the stripe using an idempotent write primitive.

Abstract: An example device in accordance with an aspect of the present disclosure includes a redundancy controller and/or memory module to prevent data corruption and single point of failure in a fault-tolerant memory fabric. Devices include engines to issue and/or respond to primitive requests, identify failures and/or fault conditions, and receive and/or issue containment mode indications.

Abstract: According to an example, a failed component in a fault-tolerant memory fabric may be determined by transmitting request packets along a plurality of routes between the redundancy controller and a media controller in periodic cycles. The redundancy controller may determine whether route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles. In response to determining that route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles, the media controller is established as failed. In response to determining that route failures for less than all of the plurality of routes have occurred within the number of consecutive periodic cycles, a fabric device is established as failed.

Abstract: A system includes a central processing unit (CPU) to process data. A first memory management unit (MMU) in the CPU generates an external request to a bus for data located external to the CPU. An external fault handler in the CPU processes a fault response received via the bus. The fault response is generated externally to the CPU and relates to a fault being detected with respect to the external request.

Abstract: According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.