Patents by Inventor Derek Bachand
Derek Bachand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11372757Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: GrantFiled: September 4, 2020Date of Patent: June 28, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael B. Mitchell, Michael P. Wilson
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Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
Patent number: 11354239Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: GrantFiled: September 18, 2020Date of Patent: June 7, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson -
MAINTAINING DOMAIN COHERENCE STATES INCLUDING DOMAIN STATE NO-OWNED (DSN) IN PROCESSOR-BASED DEVICES
Publication number: 20220091979Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Eric Francis ROBINSON, Kevin Neal MAGILL, Jason PANAVICH, Derek BACHAND, Michael B. MITCHELL, Michael P. WILSON -
Publication number: 20220075726Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 11138114Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: GrantFiled: January 8, 2020Date of Patent: October 5, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael P. Wilson, Michael B. Mitchell
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Patent number: 11093396Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: GrantFiled: November 8, 2019Date of Patent: August 17, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Derek Bachand, Jason Panavich, Kevin Neal Magill, Michael B. Mitchell, Michael P. Wilson
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Publication number: 20210209026Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael P. WILSON, Michael B. MITCHELL
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Publication number: 20210141726Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventors: Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Kevin Neal MAGILL, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 8205111Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.Type: GrantFiled: January 2, 2009Date of Patent: June 19, 2012Assignee: Intel CorporationInventors: David L. Hill, Robert J. Greiner, Tim Frodsham, Derek Bachand, Anant Deval, Mark Waggoner
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Publication number: 20100174936Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.Type: ApplicationFiled: January 2, 2009Publication date: July 8, 2010Inventors: David L. Hill, Robert J. Greiner, Tim Frodsham, Derek Bachand, Anant Deval, Mark Waggoner
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Publication number: 20070094462Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.Type: ApplicationFiled: November 7, 2006Publication date: April 26, 2007Applicant: INTEL CORPORATIONInventors: David HILL, Derek BACHAND
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Publication number: 20070073977Abstract: In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2005Publication date: March 29, 2007Inventors: Robert Safranek, Robert Greiner, David Hill, Buderya Acharya, Zohar Bogin, Derek Bachand, Robert Beers
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Publication number: 20050268051Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.Type: ApplicationFiled: May 11, 2004Publication date: December 1, 2005Applicant: INTEL CORPORATIONInventors: David Hill, Derek Bachand
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Patent number: 6378048Abstract: A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled “SLIME.” The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status.Type: GrantFiled: November 12, 1998Date of Patent: April 23, 2002Assignee: Intel CorporationInventors: Chinna Prudvi, Paul Breuder, Quinn W. Merrill, Derek Bachand, Harish kumar Kumar, Brent E. Lince