Abstract: A host device establishes a wireless communication link with a client device, and implements a wired communication standard on the link to transfer a first data stream. To increase data throughput while complying with the standard, the host device replaces synchronizing information in a packet to be sent during a first synchronizing frame with configuration information indicating that packet exchange data of a second data stream is to be sent or received during a second synchronizing frame. The host device sends or receives the packet exchange data of the second data stream to or from the client device during the second synchronizing frame via the wireless communication link. The host device may send or receive the packet exchange data of the second data stream during delays or idle periods between sending and/or receiving packets of the first data stream via the wireless communication link according to the wired communication standard.

Abstract: A host device establishes a wireless communication link with a client device, and implements a wired communication standard on the link to transfer a first data stream. To increase data throughput while complying with the standard, the host device replaces synchronizing information in a packet to be sent during a first synchronizing frame with configuration information indicating that packet exchange data of a second data stream is to be sent or received during a second synchronizing frame. The host device sends or receives the packet exchange data of the second data stream to or from the client device during the second synchronizing frame via the wireless communication link. The host device may send or receive the packet exchange data of the second data stream during delays or idle periods between sending and/or receiving packets of the first data stream via the wireless communication link according to the wired communication standard.

Abstract: A host device establishes a wireless communication link with a client device, and implements a wired communication standard on the link to transfer a first data stream. To increase data throughput while complying with the standard, the host device replaces synchronizing information in a packet to be sent during a first synchronizing frame with configuration information indicating that packet exchange data of a second data stream is to be sent or received during a second synchronizing frame. The host device sends or receives the packet exchange data of the second data stream to or from the client device during the second synchronizing frame via the wireless communication link. The host device may send or receive the packet exchange data of the second data stream during delays or idle periods between sending and/or receiving packets of the first data stream via the wireless communication link according to the wired communication standard.

Abstract: Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.

Abstract: Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

Abstract: At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.