Patents by Inventor Derek Gerstmann

Derek Gerstmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12393423
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: August 19, 2025
    Assignee: Intel Corporation
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20240329997
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Application
    Filed: February 6, 2024
    Publication date: October 3, 2024
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11941400
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11507838
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Mikael Bourges-Sevenier, Adam Herr, Sridhar Sharma, Derek Gerstmann, Todd Anderson, Justin Gottschlich
  • Publication number: 20220171626
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11269639
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 10908884
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20190324755
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 24, 2019
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20190325314
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Mikael Bourges-Sevenier, Adam Herr, Sridhar Sharma, Derek Gerstmann, Todd Anderson, Justin Gottschlich
  • Publication number: 20190317880
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve runtime performance of software executing on a heterogeneous system. An example apparatus includes a feedback interface to collect a performance characteristic of the heterogeneous system associated with a compiled version of a block of code at a first runtime, the compiled version executed according to a function designating successful execution of the compiled version on the heterogeneous system, the heterogeneous system including a first processing element and a second processing element different than the first processing element; a performance analyzer to determine a performance delta based on the performance characteristic and the function; and a machine learning modeler to, prior to a second runtime, adjust a cost model of the first processing element based on the performance delta, the adjusted cost model to cause a reduction in the performance delta to improve runtime performance of the heterogeneous system.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Derek Gerstmann, Justin Gottschlich
  • Publication number: 20190317740
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma