Patents by Inventor Derek H. Leu
Derek H. Leu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9503091Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage.Type: GrantFiled: November 20, 2013Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Toshiaki Kirihata, Derek H. Leu, Ming Yin
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Patent number: 9497027Abstract: Described are a hardware encryption engine, and secret key registration and authentication system recoverable binary bit using knowing an initial secret key stored in the master system. The secret key is overwritten in each authentication, updating it to the master and encryption engine independently. The secret key over write command can be preferably given to the chip as a CHG, and the non recoverable binary bit from the sense amplifier is used for response.Type: GrantFiled: June 2, 2014Date of Patent: November 15, 2016Assignee: GlobalFoundries, Inc.Inventors: Xiang Chen, Derek H. Leu, Toshiaki Kirihata, Sami Rosenblatt
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Patent number: 9436845Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.Type: GrantFiled: March 25, 2014Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Sami Rosenblatt
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Patent number: 9418745Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.Type: GrantFiled: March 18, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Xiang Chen, Toshiaki Kirihata, Derek H. Leu, Dan Moy
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Patent number: 9355739Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices.Type: GrantFiled: November 20, 2013Date of Patent: May 31, 2016Assignee: Globalfoundries Inc.Inventors: Pamela Castalino, Toshiaki Kirihata, Derek H. Leu
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Publication number: 20150349967Abstract: Described are a hardware encryption engine, and secret key registration and authentication system recoverable binary bit using knowing an initial secret key stored in the master system. The secret key is overwritten in each authentication, updating it to the master and encryption engine independently. The secret key over write command can be preferably given to the chip as a CHG, and the non recoverable binary bit from the sense amplifier is used for response.Type: ApplicationFiled: June 2, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Xiang Chen, Derek H. Leu, Toshiaki Kirihata, Sami Rosenblatt
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Publication number: 20150278551Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.Type: ApplicationFiled: March 25, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Sami Rosenblatt
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Publication number: 20150138868Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pamela Castalino, Toshiaki Kirihata, Derek H. Leu
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Publication number: 20150138891Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: International Business Machiness CorporationInventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
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Publication number: 20150138867Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiaki Kirihata, Derek H. Leu, Ming Yin
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Patent number: 9025386Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.Type: GrantFiled: November 20, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
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Patent number: 8872322Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.Type: GrantFiled: October 22, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Kevin W. Gorman, Derek H. Leu, Krishnendu Mondal, Saravanan Sethuraman
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Publication number: 20140110711Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.Type: ApplicationFiled: October 22, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin W. Gorman, Derek H. Leu, Krishnendu Mondal, Saravanan Sethuraman
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Patent number: 8120968Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.Type: GrantFiled: February 12, 2010Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: William Robert Reohr, John Edward Barth, Jr., Toshiaki Kirihata, Derek H. Leu, Donald W. Plass
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Publication number: 20110199837Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: International Business Machines CorporationInventors: William Robert Reohr, John Edward Barth, JR., Toshiaki Kirihata, Derek H. Leu, Donald W. Plass