Patents by Inventor Derek Hower
Derek Hower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11221971Abstract: Systems and methods are directed to managing access to a shared memory. A request received at a memory controller, for access to the shared memory from a client of one or more clients configured to access the shared memory, is placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request, based, at least in part on a priority associated with the client which generated the request. The priority may be fixed or based on a Quality-of-Service (QoS) class of the client. A timer is incremented while the request remains in the first queue. As the timer traverses each one of the one or more timeout values in the series, a criticality level of the request is incremented. A request with a higher criticality level may be prioritized for servicing over a request with a lower criticality level.Type: GrantFiled: September 23, 2016Date of Patent: January 11, 2022Assignee: Qualcomm IncorporatedInventors: Derek Hower, Harold Wade Cain, III, Carl Alan Waldspurger
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Patent number: 10838731Abstract: Branch prediction methods and systems include, for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table comprises at least a tag field, and an accuracy counter. For a tag hit at an entry indexed by the PC value, if a value of the corresponding accuracy counter is greater than or equal to zero, a prediction counter from a prediction counter pool is selected based on a function of the PC value and a load-path history, wherein the prediction counters comprise respective confidence values and prediction values. A memory-dependent branch prediction of the branch instruction is assigned as the prediction value of the selected prediction counter if the associated confidence value is greater than zero, while branch prediction from a conventional branch predictor is overridden.Type: GrantFiled: September 19, 2018Date of Patent: November 17, 2020Assignee: Qualcomm IncorporatedInventors: Rami Mohammad A. Al Sheikh, Michael Scott McIlvaine, Robert Douglas Clancy, Derek Hower
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Publication number: 20200089504Abstract: Branch prediction methods and systems include, for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table comprises at least a tag field, and an accuracy counter. For a tag hit at an entry indexed by the PC value, if a value of the corresponding accuracy counter is greater than or equal to zero, a prediction counter from a prediction counter pool is selected based on a function of the PC value and a load-path history, wherein the prediction counters comprise respective confidence values and prediction values. A memory-dependent branch prediction of the branch instruction is assigned as the prediction value of the selected prediction counter if the associated confidence value is greater than zero, while branch prediction from a conventional branch predictor is overridden.Type: ApplicationFiled: September 19, 2018Publication date: March 19, 2020Inventors: Rami Mohammad A. AL SHEIKH, Michael Scott MCILVAINE, Robert Douglas CLANCY, Derek HOWER
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Patent number: 10379863Abstract: Systems and methods for constructing an instruction slice for prefetching data of a data-dependent load instruction include a slicer for identifying a load instruction in an instruction sequence as a first occurrence of a qualified load instruction which will miss in a last-level cache. A commit buffer stores information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow. For a second occurrence of the qualified load instruction, an instruction slice is constructed from the information in the commit buffer to form a slice payload. A pre-execution engine pre-executes the instruction slice based on the slice payload to determine an address from which data is to be fetched for execution of a third and any subsequent occurrences of the qualified load instruction. The data is prefetched from the determined address for the third and any subsequent occurrence of the qualified load instruction.Type: GrantFiled: September 21, 2017Date of Patent: August 13, 2019Assignee: QUALCOMM IncorporatedInventors: Shivam Priyadarshi, Rami Mohammad A. Al Sheikh, Brandon Dwiel, Derek Hower
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Patent number: 10303608Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.Type: GrantFiled: August 22, 2017Date of Patent: May 28, 2019Assignee: QUALCOMM IncorporatedInventors: Rami Mohammad Al Sheikh, Shivam Priyadarshi, Brandon Dwiel, David John Palframan, Derek Hower, Muntaquim Faruk Chowdhury
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Publication number: 20190087192Abstract: Systems and methods for constructing an instruction slice for prefetching data of a data-dependent load instruction include a slicer for identifying a load instruction in an instruction sequence as a first occurrence of a qualified load instruction which will miss in a last-level cache. A commit buffer stores information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow. For a second occurrence of the qualified load instruction, an instruction slice is constructed from the information in the commit buffer to form a slice payload. A pre-execution engine pre-executes the instruction slice based on the slice payload to determine an address from which data is to be fetched for execution of a third and any subsequent occurrences of the qualified load instruction. The data is prefetched from the determined address for the third and any subsequent occurrence of the qualified load instruction.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Shivam PRIYADARSHI, Rami Mohammad A. AL SHEIKH, Brandon DWIEL, Derek HOWER
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Publication number: 20190065375Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Rami Mohammad AL SHEIKH, Shivam PRIYADARSHI, Brandon DWIEL, David John PALFRAMAN, Derek HOWER, Muntaquim Faruk CHOWDHURY
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Publication number: 20190065964Abstract: A method and apparatus for predicting instruction load values in a processor. While a program is executing the processor is used to train predictors in order to predict load values. In particular 4 differing kinds of predictors are trained. The four predictors are the Last Value Predictor (LVP) which captures loads that encounter very few values, the Stride Address Predictor (SAP) which captures loads based on stride (offset) addresses, a Content Address Predictor (CAP) which captures load addresses that are non-stride and the Context Value Predictor (CVP) which captures load values in a particular context that are non-stride. Training methods and the use of such predictors are disclosed.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Rami Mohammad A. AL SHEIKH, Derek HOWER
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Publication number: 20190065384Abstract: A request to access data at a first physical address misses in a private cache of a processor. A confidence value is received for the first physical address based on a hash value of the first physical address. A determination is made that the received confidence value exceeds a threshold value. In response, a speculative read request specifying the first physical address is issued to a memory controller of a main memory to expedite a miss for the data at the first physical address in a shared cache.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Rami Mohammad AL SHEIKH, Shivam PRIYADARSHI, Brandon DWIEL, David John PALFRAMAN, Derek HOWER
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Publication number: 20170293578Abstract: Systems and methods are directed to managing access to a shared memory. A request received at a memory controller, for access to the shared memory from a client of one or more clients configured to access the shared memory, is placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request, based, at least in part on a priority associated with the client which generated the request. The priority may be fixed or based on a Quality-of-Service (QoS) class of the client. A timer is incremented while the request remains in the first queue. As the timer traverses each one of the one or more timeout values in the series, a criticality level of the request is incremented. A request with a higher criticality level may be prioritized for servicing over a request with a lower criticality level.Type: ApplicationFiled: September 23, 2016Publication date: October 12, 2017Inventors: Derek HOWER, Harold Wade CAIN, III, Carl Alan WALDSPURGER
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Patent number: 9746908Abstract: A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information stored to memory.Type: GrantFiled: February 25, 2015Date of Patent: August 29, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Derek Hower, Marc Orr
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Publication number: 20160246360Abstract: A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information stored to memory.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: Yasuko Eckert, Derek Hower, Marc Orr