Abstract: A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N?1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N?1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N?1, N, and N+1.

Abstract: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N?1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N?1, N, and N+1 to a table stored in the memory device.

Abstract: A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Abstract: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N?1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N?1, N, and N+1 to a table stored in the memory device.

Abstract: A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N-1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N-1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N-1, N, and N+1.

Abstract: A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Abstract: A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.

Abstract: The preferred embodiments described herein provide a method for reading data in a write-once memory device using a write-many file system. In one preferred embodiment, data traffic between a data storage device and a write-once memory device is redirected so that file system structures of a write-many file system do not overwrite previously-stored file system structures. Data traffic between the write-once storage device and a data reading device is also redirected so that a current file system structure of the write-many file system is provided to the data reading device instead of an out-of- date file system structure. In another preferred embodiment, a non-volatile write-many memory array is provided in the write-once memory device to store file system structures of a write-many file system.

Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The preferred embodiments described herein provide a memory device and method for storing bits in non-adjacent storage locations in a memory array. In one preferred embodiment, a memory device is provided comprising a register and a memory array. A plurality of bits provided to the memory device are stored in the register in a first direction, read from the register in a second direction, and then stored in the memory array. Bits that are adjacent to one another when provided to the memory device are stored in non-adjacent storage locations in the memory array. When the plurality of bits takes the form of an ECC word, the storage of bits in non-adjacent storage locations in the memory array reduces the likelihood of an uncorrectable multi-bit error. In another preferred embodiment, a memory device is provided comprising a memory array and a register comprising a first set of wordlines and bitlines and a second set of wordlines and bitlines arranged orthogonal to the first set.

Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.

Abstract: A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: An acquisition/playback device and a memory device including a solid-state write-once memory array are used to acquire and display digital information such as digital images, voice, music, or the like. Prior to display or other presentation, the digital information is stored in a re-writable memory. After the digital information has been displayed or otherwise presented to the user for review, the user then elects whether to store the digital information in the write-once memory array. Depending upon the user election, the digital information is either stored in the write-once memory array, or erased from the re-writable memory without being stored in the write-once memory array. In this way the limited storage capacity of the write-once memory array is preserved for digital information that is of long-term interest to the user.

Abstract: The preferred embodiments described herein provide a memory device and method for storing bits in non-adjacent storage locations in a memory array. In one preferred embodiment, a memory device is provided comprising a register and a memory array. A plurality of bits provided to the memory device are stored in the register in a first direction, read from the register in a second direction, and then stored in the memory array. Bits that are adjacent to one another when provided to the memory device are stored in non-adjacent storage locations in the memory array. When the plurality of bits takes the form of an ECC word, the storage of bits in non-adjacent storage locations in the memory array reduces the likelihood of an uncorrectable multi-bit error. In another preferred embodiment, a memory device is provided comprising a memory array and a register comprising a first set of wordlines and bitlines and a second set of wordlines and bitlines arranged orthogonal to the first set.

Abstract: A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.

Abstract: A write-once memory device includes a memory array controller and an electronically resetable flag. The memory array controller prevents writing and erasing from a write-once memory array unless the flag is in a selected state. The memory device is used with a data storage system that automatically determines whether a memory device installed in the data storage system is a write-once memory, and then automatically sends a recognition signal to the memory device once it has been determined to be a write-once memory. The memory device (1) automatically sets the flag in response to the recognition signal, (2) automatically refuses to implement write and erase commands prior to receipt of the recognition signal and setting of the flag, and (3) implements write and erase commands subsequent to receipt of the recognition signal and setting of the flag. The memory device implements nondestructive commands such as read and status commands regardless of the state of the flag.