Patents by Inventor Derek J. Gochnour

Derek J. Gochnour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090243012
    Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Derek J. Gochnour, Alan G. Wood, James M. Derderian, Luke G. England, Owen R. Fay
  • Publication number: 20090243051
    Abstract: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Alan G. Wood, James M. Derderian, Derek J. Gochnour, Owen R. Fay, Luke G. England
  • Patent number: 7561938
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 7387119
    Abstract: A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be moved laterally or vertically, independent of one or more other blades.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 7166252
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture maybe constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 7155300
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 7120513
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 7022533
    Abstract: A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6970359
    Abstract: An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. A locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removably interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: November 29, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Walter L. Moden, Michael W. Morrison
  • Patent number: 6932077
    Abstract: A semiconductor wafer saw for dicing semiconductor wafers comprises variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: August 23, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6897571
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers including a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: May 24, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6888159
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6865086
    Abstract: An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. The locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removable interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: March 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Walter L. Moden, Michael W. Morrison
  • Patent number: 6841796
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: January 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6830719
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6808947
    Abstract: A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: October 26, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Publication number: 20040171179
    Abstract: A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 2, 2004
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6764549
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board. In the method, at least one printed circuit board is mounted to a clamping fixture support whereby a clamping fixture overlay is placed on top of the first printed circuit board.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20040089282
    Abstract: A semiconductor wafer saw for dicing semiconductor wafers comprises variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 13, 2004
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6710612
    Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dice and method for testing such dice is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dice can be reliably tested including chip scale packaged (“CSP”) BGA dice. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dice and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dice through closing the test socket before removing the die deposit probe.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour, David R. Hembree