Abstract: A GPU is disclosed, which may include a VRS interface to provide spatial information and/or primitive-specific information. The GPU may include one or more shader cores including a control logic section to determine a shading precision value based on the spatial information and/or the primitive-specific information. The control logic section may modulate a shading precision according to the shading precision value. A method for controlling shading precision by a GPU may include providing, by a VRS interface, the spatial information and/or primitive-specific information. The method may include determining, by a control logic section, a shading precision value based on the spatial information and/or the primitive-specific information. The method may include modulating a shading precision according to the shading precision value.

Abstract: A method for performing a blending operation in a graphics processing unit may include multiplying a first value and a first blend factor for a component of a render target with a first multiply operation of a multiplier, multiplying a second value and a second blend factor for the component of the render target with a second multiply operation of the multiplier, and adding a first result of the first multiply operation and a second result of the second multiply operation. The method may further include bypassing the multiplier for a first blend factor of substantially zero. The method may further include, for a blend factor of substantially one: bypassing the multiplier, and providing the first value of the component of the render target as a result of the first multiply operation.

Abstract: A method for avoiding lockup in a graphics pipeline may include accumulating position information in an accumulating stage of the pipeline, passing position information from a first preceding stage of the pipeline to the accumulating stage, determining a condition in the first preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage. The method may further include passing position information from the first preceding stage to a second preceding stage of the pipeline, passing position information from the second preceding stage to the accumulating stage, determining a condition in the second preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage and the condition in the second preceding stage.

Abstract: A method for rendering an image in a graphics processing system may include calculating texture coverage data for an image during an image coverage pass using a rendering pipeline, generating rendered texture data during a texture rendering pass in texture space based on the texture coverage data using one or more hardware resources of the rendering pipeline, and rendering the image based on the rendered texture data using the rendering pipeline. A graphics processing system may include a rendering pipeline configured to support decoupled shading, the pipeline may include a data buffer configured to receive texture coverage data for an image, and a rasterization unit configured to read the texture coverage data from the data buffer and use the texture coverage data to limit rasterization coverage during a texture rendering pass for the image.

Abstract: A method for avoiding lockup in a graphics pipeline may include accumulating position information in an accumulating stage of the pipeline, passing position information from a first preceding stage of the pipeline to the accumulating stage, determining a condition in the first preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage. The method may further include passing position information from the first preceding stage to a second preceding stage of the pipeline, passing position information from the second preceding stage to the accumulating stage, determining a condition in the second preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage and the condition in the second preceding stage.

Abstract: Provided is a method of performing coverage merging in a shading stage of a graphics system. The method includes: performing a draw call on primitives and rasterizing the primitives into blocks of pixels; selecting the draw call for merge testing of individual blocks; performing a depth test on the individual blocks; in response to the depth test being satisfied, merging partially covered fragments of the same draw call of one of the block of pixels to form a merged block of pixels; and performing shading of the merged block of pixels on a draw call basis.

Abstract: Provided is a method of performing coverage merging in a shading stage of a graphics system. The method includes: performing a draw call on primitives and rasterizing the primitives into blocks of pixels; selecting the draw call for merge testing of individual blocks; performing a depth test on the individual blocks; in response to the depth test being satisfied, merging partially covered fragments of the same draw call of one of the block of pixels to form a merged block of pixels; and performing shading of the merged block of pixels on a draw call basis.

Abstract: Fragment merging is performed on a draw call basis. One application is for quad merging. Primitives of the same draw call have many common attributes, such as a graphics state, which facilitates merging of quad fragments. Partially covered quad fragments of the same draw call are considered for possible merging and at least one merge test performed. The merge test may include error tests such as a level of detail error test, interpolated depth, and an interpolation error test.

Abstract: Fragment merging is performed on a draw call basis. One application is for quad merging. Primitives of the same draw call have many common attributes, such as a graphics state, which facilitates merging of quad fragments. Partially covered quad fragments of the same draw call are considered for possible merging and at least one merge test performed. The merge test may include error tests such as a level of detail error test, interpolated depth, and an interpolation error test.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types.

Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.