Abstract: Circuitry is employed to provide an array of photoelements for generating an electrical signal from light energy. The circuit is essentially comprised of a plurality of photoelements including a light-receiving portion, which may include a phototransistor for receiving light and generating electrical energy therefrom, and a non-light-receiving portion, which may include amplification circuitry for properly biasing the phototransistor base and for amplifying the light signal. Within the array, geometric centers of vertically and horizontally adjacent phototransistors are equidistant from one another to form a symmetrical array of photoelements. A relatively high fill factor is achieved by an efficient, symmetrical layout of the photoelements within the array. One main advantage of the high fill factor of the symmetrical array is that it generates a greater light signal than related designs, which eliminates the need for optical magnification of pixels on an original sheet of paper.

Abstract: An apparatus and method, which improves both the matching of the integral non-linearity of multiple resistor-string based DACs connected in parallel between two different reference voltages and the charge/discharge time of the parasitic capacitances associated with middle nodes of the DAC resistor strings, is presented. In a device where a plurality of DACs are connected in parallel between a first reference voltage and a second reference voltage, and each DAC is implemented using a plurality of resistors coupled in series between the two reference voltages, the resistor string in each DAC is partitioned into a plurality of subsets. A DAC node is located between each subset in each DAC, such that each DAC includes corresponding resistor subsets and corresponding DAC nodes.

Abstract: A scanning mouse has two optical navigation sensors to allow measurement of both translation and rotation of the scanning mouse. It also has an image sensor, and the ability to digitize the sensed image data. There may be a second image sensor at perpendicular to the first. A high speed digital data path connects the scanning mouse to the computer. Software in the computer processes image line data that includes the locations of the navigation sensors and the digitized image data to produce partial scanned images that are further assembled into a complete image within the environment of the computer. Each optical navigation sensor images as an array of pixels the spatial features of generally any micro textured or micro detailed work surface below the mouse. The photo detector responses are digitized and stored as a frame into memory. Motion produces successive frames of translated patterns of pixel information, which are compared by autocorrelation to ascertain the direction and amount of movement.

Abstract: A differential flash ADC includes an input follower differential input stage for receiving a differential input signal. The outputs of the differential input stage are coupled to legs of a differential resistive ladder having nodes cross-coupled to the inputs of a comparator array. Each leg of the differential resistor ladder is terminated by a current source.

Abstract: A modulator for a clock pulse generator receives clock pulses from a clock pulse source, which clock pulses exhibit a reference phase. Delay circuitry is connected to the clock pulse source and includes n tap connections, each connection providing a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer is connected to each of the n tap connections and provides an output manifesting the clock pulses. A selector circuit controls the multiplexer to sequentially connect any sequence of different ones of the n tap connections to the multiplexer's output, whereby the output manifests a series of clock pulses which have different phase displacements from the reference phase.

Abstract: A system is described that includes an integrated circuit chip having output paths connected to a network whose electrical of capacitance characteristics can vary. The system includes a circuit for adjusting output drive applied to a pad on the chip. The circuit includes a PVT monitor for providing an output that is related to process, voltage and temperature parameter variations on the chip. A processor determines network configuration information and enables the network's electrical or capacitance characteristics to be determined. The processor is responsive to an output from the PVT monitor and the network's determined electrical characteristics to provide control outputs indicative of a required output drive current level. A drive current circuit includes alterable circuitry and is responsive to the processor's control output to provide the required output drive levels to the pad.