Abstract: A process for forming low resistance ohmic contacts on indium phosphide (InP) avoids the usual problem of high temperature annealing. The method comprises passing a current between two contacts of a suitably chosen metallic conductor that is doped so as to be the same conductivity type as the underlining semiconductor. Passage of the current causes the contacts to combine with the semiconductor via field assisted thermal diffusion.

Abstract: A method for annealing semiconductor samples, especially following ion-implantation of semiconductor samples is disclosed. A furnace on a set of rails is passed over the semiconductor sample which is supported on a stationary wire basket made of low thermal mass, fine tungsten wire. The furnace temperature may be about 5.degree. above the desired anneal temperature of the semiconductor sample such that the sample temperature rises to within a few degrees of the furnace temperature within seconds. Utilizing the moveable furnace insures uniform heating without elaborate temperature control or expensive beam generating equipment.The apparatus and process of the present invention are utilized for rapid annealing of ion-implanted indium phosphide semiconductors within 10 to 30 seconds and at temperatures of approximately 700.degree. C., thereby eliminating undesired and damaging movement of impurities within the ion-implanted InP.

Abstract: A normally off insulated gate field effect transistor having a p-type sin crystal InP substrate with source and drain contacts spaced apart and disposed thereon with a layer of silicon dioxide disposed over the InP material in the space between the contacts and a gate electrode disposed on the silicon dioxide to completely bridge the space between the contacts. The p-type single crystal InP substrate may be replaced by a p-type epitaxial InP material disposed on a semi-insulating InP substrate.

Abstract: A liquid barrier contact to InP made of 40% tartatic acid and 30% hydrogen peroxide in a 3:1 ratio by volume is used for capacitance-voltage carrier profiling to large voltages (>10 V) on relatively heavily doped material (>10.sup.17 CM.sup.-3) and at room temperature.

Abstract: A method for the thinning and automatic leveling of layers of a semicondur for use in device fabrication applications. The method is to be employed with anodic thinning wherein a conducting semiconductor layer on a high resistivity substrate is placed in a suitable electrolyte and voltage is applied so that the sample is made positive with respect to a cathode, also immersed in the electrolyte. The instant method is directed to the anodic thinning of irregularities in the semiconductor by slowly immersing the semiconductor into the electrolyte such that the location of irregularities can be determined and processed by monitoring the anodic process.

Abstract: A method and apparatus of determining defects in semiconductors, by scann with small spot of light. As the semiconductor is scanned, a voltage is generated which may be used to indicate gross defects as well as the reduction in carrier lifetime due to the defects.