Abstract: A technique of authenticating a person involves obtaining, during a current authentication session to authenticate the person, a first authentication factor from the person and a second authentication factor from the person, at least one of the first and second authentication factors being a biometric input. The technique further involves performing an authentication operation which cross references the first authentication factor with the second authentication factor. The technique further involves outputting, as a result of the authentication operation, an authentication result signal indicating whether the authentication operation has determined the person in the current authentication session likely to be legitimate or an imposter. Such authentication, which cross references authentication factors to leverage off of their interdependency, provides stronger authentication than conventional naïve authentication.

Abstract: An improved technique trains a fraud detection system to use mouse movement data as part of a user profile. Along these lines, a training apparatus receives sets of mouse movement datasets generated by a legitimate user and/or a fraudulent user. The training apparatus assigns each mouse movement dataset to a cluster according to one of several combinations of representations, distance metrics, and cluster metrics. By correlating the clusters with the origins of the mouse movement datasets (legitimate or fraudulent user), the training apparatus constructs a robust framework for detecting fraud at least partially based on mouse movement data.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.

Abstract: Improved techniques involve controlling access to data based on who has previously accessed the data. For example, when a user submits a request to access a resource, a list of those users who have accessed the resource is generated. Identifiers associated with the requesting user and the accessing users from the list of users are located within an organization chart which contains information about the hierarchal level and department to which users within the organization belong. As an example, if the requesting user is an executive-level employee and the accessing users are also executive-level users, then access to the resource is granted. If, on the other hand, the requesting user is on the level of an individual contributor, or a contractor, then access to the resource is denied. Further, access requests can be recorded in the access log for tracking.

Abstract: A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Abstract: An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

Abstract: An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.