Abstract: An apparatus comprises a first data line coupled to a first driver; a second data line coupled to a second driver; and a crosstalk cancelation circuit comprising a third driver coupled between the first data line and the second data line, the crosstalk cancelation circuit to compensate for far end crosstalk introduced from the first data line to the second data line.

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract: A method and apparatus for transceiver clock architecture with transmit PLL and receive slave delay lines. In one embodiment, the method includes the generation of a transmitter (Tx) clock signal by adjusting a control voltage of a voltage controlled oscillator to lock a phase and frequency of Tx clock signal to a reference clock signal. In one embodiment, a frequency of the Tx clock signal is a multiple of a frequency of the reference clock signal. In one embodiment, a slave delay line may be used, including a plurality of variable delay buffers that are configured according to the control voltage to generate a receiver (Rx) clock signal in response to a received clock signal that is synchronized with the reference clock signal. The Rx clock signal may be provided to data recovery logic to sample data. Other embodiments are described and claimed.

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract: Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.

Abstract: Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.

Abstract: A method and apparatus for transceiver clock architecture with transmit PLL and receive slave delay lines. In one embodiment, the method includes the generation of a transmitter (Tx) clock signal by adjusting a control voltage of a voltage controlled oscillator to lock a phase and frequency of Tx clock signal to a reference clock signal. In one embodiment, a frequency of the Tx clock signal is a multiple of a frequency of the reference clock signal. In one embodiment, a slave delay line may be used, including a plurality of variable delay buffers that are configured according to the control voltage to generate a receiver (Rx) clock signal in response to a received clock signal that is synchronized with the reference clock signal. The Rx clock signal may be provided to data recovery logic to sample data. Other embodiments are described and claimed.