Abstract: A random access memory apparatus suitable for sequential write/non-sequential read, for example in a digital video special effects unit, comprises a write enable demultiplexer and a write address generator for demultiplexing incoming data into N channels A to D, where N is at least two, N memories in each of the N channels A to D, the incoming data allocated to any given one of the channels A to D being written into all of the memories in the given channel A to D, a read address generator for reading stored data from any one of the memories and, on reading from a memory, setting a busy flag for that memory, the busy flag being cleared N data periods later, and a busy flag control to control the read address generator to step onto a different memory in the same channel A to D as a memory to be read, when the memory to be read has a set busy flag. Apparatus is also provided for non-sequential write/sequential read and non-sequential write/non-sequential read.

Abstract: A flight simulator includes a host computer 10 coupled to serial buses 13 by master-interface circuits 12, each of which is a serial bus master controller. Each bus 13 is coupled to a number of slave circuits 14, and each slave circuit 14 drives several instrument display devices 15. The slave circuits 14 contain slave bus controllers and digital to analog conversion circuits for developing the drive signals for the display devices 15. Each slave bus controller is provided with one or more programs for processing received serial data in accordance with the electro-mechanical characteristics of the driven display device 15. Analog feedback signals may be provided by the devices 15 and A-D converted in the respective slave circuits 14 before transmission as serial data to the host computer 10 via the buses 13 and master-interfaces 12.