Patents by Inventor Derek Pappas
Derek Pappas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922101Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: March 20, 2023Date of Patent: March 5, 2024Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20230310962Abstract: A training device for a game of stick and ball, such as filed hockey. The training device can mount to a standard hockey stick to guide the movements and limit certain movements and spatial positions of the hockey stick while practicing. The training device includes a disc having a central section and a peripheral rim; a sleeve in the central section receives a handle and a shaft of a stick; and a fastening member coupled to the sleeve and secures the training device to a head or the shaft of the stick that is within the sleeve.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventor: Derek Pappas
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Publication number: 20230237217Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: March 20, 2023Publication date: July 27, 2023Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Patent number: 11610036Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: June 28, 2021Date of Patent: March 21, 2023Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20210365609Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: June 28, 2021Publication date: November 25, 2021Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Patent number: 11048838Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: August 1, 2019Date of Patent: June 29, 2021Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20200042664Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: August 1, 2019Publication date: February 6, 2020Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Patent number: 8705630Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.Type: GrantFiled: December 8, 2006Date of Patent: April 22, 2014Assignee: NVIDIA CorporationInventors: Derek Pappas, Atul Garg, Shankar Moni, Harikrishna M. Reddy, Matthew R. Longnecker, Christopher L. Mills, Ignatius B. Tjandrasuwita
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Publication number: 20070189390Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.Type: ApplicationFiled: December 8, 2006Publication date: August 16, 2007Inventors: Derek Pappas, Atul Garg, Shankar Moni, Harikrishna M. Reddy, Matthew R. Longnecker, Christopher L. Mills, Ignatius B. Tjandrasuwita
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Publication number: 20030188302Abstract: A method and apparatus for detecting and decomposing component loops in a logic design is described. The invention first detects any component loops when the compiler schedules the processing order of the combinational logic components in the digital circuit design. To identify component loops, the compiler levelizes the design and sorts the combinational logic components, making sure that no true combinational logic loops exist. If the sorting fails, a component loop exists, and the compiler identifies such components and selects one or more of the components to be split. Next, the invention corrects the component loops by splitting a component into multiple sub-components. By splitting a component into multiple sub-components, the output of the split component no longer provides input to another component, and hence, the component loop is broken.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Inventors: Liang T. Chen, Jeffrey Broughton, Derek Pappas