Abstract: A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

Abstract: An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Abstract: A multiplexor having a multiplexor control input terminal for selectively providing one of a plurality of conductor voltage levels to a conductor. The multiplexor includes a first switch, which is coupled to the conductor, for providing a first conductor voltage level to the conductor. A second switch is also included and coupled to the conductor for providing a second conductor voltage level to the conductor. To provide a selective discharge path for the conductor during switching, the multiplexor further includes a third switch coupled to the conductor. A discharge circuit is also provided and coupled to the conductor and the third switch for sensing the voltage level of the conductor to turn on the third switch as necessary at the early stage of switching among conductor voltage levels.

Abstract: A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

Abstract: A sense amplifier is provided that automatically determines its enabled/disabled state. The sense amplifier includes a latch to store the enable/disable signals. A global power-on-reset signal during initialization sets the state of this latch to a default configuration which disables, i.e. powers down, the sense amplifier. During configuration, an active latch enable signal forces the sense amplifier into an enable ready state. Then, a high signal is provided to each wordline associated with the bitline of the sense amplifier. This causes any erased memory cell driven by the wordlines to pull the associated bitline into a bitline low state and causes the sense amplifier output signal to switch states. This switch causes the latch to be overwritten with the opposite state, thereby enabling the sense amplifier. When the latch enable signal goes inactive after configuration of the device, the latch is set such that the sense amplifier remains enabled, i.e. powered up.

Abstract: A programmable logic device (PLD) performs a self-test erase check operation on memory elements to verify if the PLD is completely erased. The output signals of the sense amplifiers associated with the PLD bitlines drive a plurality of NMOS devices. The NMOS devices share a common source (node), thereby providing in effect an n-input NOR gate, where n is the number of bitlines in the array. The memory cells associated with an entire wordline of the PLD memory array are simultaneously checked for an erased state by bringing the wordline under test high while keeping all other wordlines low. If all of the memory cells on a wordline are erased, every sense amplifier output is low, all of the NMOS devices are off, and the output signal of the NOR gate is high due to a weak pull-up on the common node, thereby indicating that the whole column is properly erased.