Patents by Inventor Derek Roberts
Derek Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147799Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.Type: ApplicationFiled: November 3, 2023Publication date: May 8, 2025Applicant: Xilinx, Inc.Inventors: Thomas Calvert, Ripduman Sohan, Dmitri Kitariev, Kimon Karras, Stephan Diestelhorst, Neil Turton, David Riddoch, Derek Roberts, Kieran Mansley, Steven Pope
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Patent number: 12224954Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.Type: GrantFiled: October 29, 2021Date of Patent: February 11, 2025Assignee: XILINX, INC.Inventors: Steven L. Pope, Dmitri Kitariev, Derek Roberts
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Patent number: 11759278Abstract: A protective cover (800) for a medical device includes a body (700) and a cap (100) that is selectively attachable to the body. The cap 100 includes an annulus 101 and a rounded vault (102) spanning an interior portion (118) of the annulus. The rounded vault defines a convex exterior (301). A plurality of partial arch trusses (103,104,105,106,107,108,109) extends from the annulus along the convex exterior toward an apex (601) of the convex exterior. Distal ends (613,614,615,616,617,618,619) of the plurality of partial arch trusses define an interstice (611) at the apex. The partial arch trusses provide longitudinal deflection of impact forces to protect the medical device.Type: GrantFiled: December 19, 2018Date of Patent: September 19, 2023Assignee: Medline Industries, LPInventors: Christina Finley, Michael Turturro, Timur Selimkhanov, Derek Roberts, Sean Kroll
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Patent number: 11693777Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: GrantFiled: October 4, 2021Date of Patent: July 4, 2023Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Patent number: 11695669Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.Type: GrantFiled: May 24, 2021Date of Patent: July 4, 2023Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11583622Abstract: A canister lid (101) for a canister (102) includes an annular perimeter (103) surrounding an interior portion (104). Rather than completely surrounding the interior portion, the annular perimeter is instead interrupted by a suction conduit (112) defined by a suction conduit (112) separating a first lobe (117) and a second lobe (118). The suction conduit (112) intersects the annular perimeter such that the first lobe is disposed interior of the annular perimeter while the second lobe is disposed exterior to the annular perimeter. The canister lid can further include one or more ports (110,111) extending from the interior portion. A canister (102) can include a valve (401) and can optionally be coupled to a hub mount vacuum source (1200) or a hub mount stand (1800).Type: GrantFiled: February 11, 2020Date of Patent: February 21, 2023Assignee: Medline Industries, LPInventors: Derek Roberts, Brian Barkeley, Zach Zott, Stuart Mintz, Thomas D. Mills
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Publication number: 20230006945Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.Type: ApplicationFiled: July 18, 2022Publication date: January 5, 2023Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch, Dmitri Kitariev
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Publication number: 20220400147Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.Type: ApplicationFiled: July 18, 2022Publication date: December 15, 2022Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch
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Patent number: 11489876Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.Type: GrantFiled: March 11, 2020Date of Patent: November 1, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11409569Abstract: A data processing system being configured to select between different hardware resources for the running of an application configured for the sending and receiving of data over a network. The selection of hardware resources may be between resources on the network interface device, and hardware resources on the host. The selection of hardware resources may be between first and second hardware resources on the network interface device. An API is provided in the data processing system that responds to requests from the application irrespective of the hardware on which the application is executing.Type: GrantFiled: March 29, 2018Date of Patent: August 9, 2022Assignee: XILINX, INC.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11394768Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.Type: GrantFiled: May 14, 2020Date of Patent: July 19, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch
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Patent number: 11394664Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.Type: GrantFiled: May 8, 2020Date of Patent: July 19, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch, Dmitri Kitariev
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Publication number: 20220060434Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.Type: ApplicationFiled: October 29, 2021Publication date: February 24, 2022Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Dmitri Kitariev, Derek Roberts
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Publication number: 20220027273Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Patent number: 11165683Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.Type: GrantFiled: December 20, 2016Date of Patent: November 2, 2021Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11165720Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.Type: GrantFiled: December 19, 2017Date of Patent: November 2, 2021Assignee: XILINX, INC.Inventors: Steven L. Pope, Dmitri Kitariev, Derek Roberts
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Patent number: 11154176Abstract: A mop (100) includes a mop head (101) having a housing (302) defining a major surface to couple to a cleaning pad (204). One or more flappers (201,202) are disposed along the major surface. The flappers, in response to actuation of an actuator (104), selectively pivot from a closed position disposed within the housing and substantially parallel with the major surface to an angularly displaced open position extending distally outward from the major surface. A user actuates the actuator (104) to detach the cleaning pad from the major surface without having to handle the cleaning pad.Type: GrantFiled: March 16, 2016Date of Patent: October 26, 2021Assignee: Medline Industries, Inc.Inventor: Derek Roberts
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Patent number: 11138116Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: GrantFiled: July 29, 2019Date of Patent: October 5, 2021Assignee: XILINX, INC.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Patent number: D980643Type: GrantFiled: November 18, 2020Date of Patent: March 14, 2023Assignee: Medline Industries, LPInventors: Xin Xu, Paige Wexler, Derek Roberts, Tamara L. Dick, Megan Henken
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Patent number: D1002006Type: GrantFiled: June 30, 2020Date of Patent: October 17, 2023Assignee: Medline Industries, LPInventors: Saul Godinez, Michael Turturro, Darin Decker, Karen Daunov, Greg Corey, Derek Roberts