Patents by Inventor Derek Robertson
Derek Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10455840Abstract: A bread product and method of manufacturing the artisan bread product that eliminates or reduces the need to proof dough after thawing is discussed. One example method comprises mixing ingredients to create a dough, bulk fermenting the dough to create a non-uniform cell structure and to eliminate or reduce proofing after receipt by a restaurant, sheeting the dough, a sheeter being adjusted to allow dough sheeting while substantially maintaining the cell structure, portioning the sheeted dough into portions according to desired sizes while substantially maintaining the cell structure, freezing the portions to create frozen portions, and packaging and shipping the frozen portions while substantially maintaining the cell structure, the bulk fermenting of the dough prior to the sheeting thereby enabling, at least in part, a restaurant to receive the frozen portions, to retard thawed portions of dough, and to bake the portions of dough after retarding without proofing.Type: GrantFiled: February 25, 2016Date of Patent: October 29, 2019Assignee: Aryzta LLCInventor: Derek Robertson
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Patent number: 9894773Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.Type: GrantFiled: December 17, 2013Date of Patent: February 13, 2018Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Derek Robertson, Vincent M. Rogers
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Publication number: 20160242423Abstract: A bread product and method of manufacturing the artisan bread product that eliminates or reduces the need to proof dough after thawing is discussed. One example method comprises mixing ingredients to create a dough, bulk fermenting the dough to create a non-uniform cell structure and to eliminate or reduce proofing after receipt by a restaurant, sheeting the dough, a sheeter being adjusted to allow dough sheeting while substantially maintaining the cell structure, portioning the sheeted dough into portions according to desired sizes while substantially maintaining the cell structure, freezing the portions to create frozen portions, and packaging and shipping the frozen portions while substantially maintaining the cell structure, the bulk fermenting of the dough prior to the sheeting thereby enabling, at least in part, a restaurant to receive the frozen portions, to retard thawed portions of dough, and to bake the portions of dough after retarding without proofing.Type: ApplicationFiled: February 25, 2016Publication date: August 25, 2016Inventor: Derek Robertson
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Patent number: 9347984Abstract: An apparatus includes a top plate and an extension card surrounding a space for a small electronic assembly. The extension card and small electronic assembly are mounted to the top plate. The apparatus includes a plurality of test probes extending through the top plate and moving relative to the top plate. A portion of the test probes are positioned to contact the extension card and a portion are positioned to contact the small electronic assembly when the test probes move with respect to the top plate. The apparatus includes a vacuum box in contact with the top plate and surrounding the extension card and small electronic assembly. The top plate moves relative to the test probes so the test probes contact the extension card and the small electronic assembly in response to a vacuum force evacuating an area under the top plate and within the vacuum box.Type: GrantFiled: July 25, 2014Date of Patent: May 24, 2016Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.Inventors: Willie T Davis, Jr., Larry G Pymento, Derek Robertson
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Publication number: 20160025804Abstract: An apparatus includes a top plate and an extension card surrounding a space for a small electronic assembly. The extension card and small electronic assembly are mounted to the top plate. The apparatus includes a plurality of test probes extending through the top plate and moving relative to the top plate. A portion of the test probes are positioned to contact the extension card and a portion are positioned to contact the small electronic assembly when the test probes move with respect to the top plate. The apparatus includes a vacuum box in contact with the top plate and surrounding the extension card and small electronic assembly. The top plate moves relative to the test probes so the test probes contact the extension card and the small electronic assembly in response to a vacuum force evacuating an area under the top plate and within the vacuum box.Type: ApplicationFiled: July 25, 2014Publication date: January 28, 2016Inventors: Willie T. Davis, JR., Larry G. Pymento, Derek Robertson
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Publication number: 20150173201Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Derek Robertson, Vincent M. Rogers
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Patent number: 8635488Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: GrantFiled: November 8, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
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Publication number: 20130117601Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
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Apparatus, system, and method for reducing power consumption on devices with multiple power supplies
Patent number: 7906871Abstract: A load module determines that a load of an electronic device is operating at a power level below a predetermined power threshold. The electronic device is configured to receive power simultaneously from two or more redundant power supplies. Each redundant power supply configured to receive input power from one or more power sources and configured to provide regulated output power to the load of the electronic device. A disconnection module disconnects at least one of the two or more redundant power supplies from the one or more power sources in response to the load module determining that the load of the electronic device is operating at a power level below the predetermined power threshold.Type: GrantFiled: December 30, 2008Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Joseph W. Freeman, Randhir S. Malik, Derek Robertson -
APPARATUS, SYSTEM, AND METHOD FOR REDUCING POWER CONSUMPTION ON DEVICES WITH MULTIPLE POWER SUPPLIES
Publication number: 20100164292Abstract: A load module determines that a load of an electronic device is operating at a power level below a predetermined power threshold. The electronic device is configured to receive power simultaneously from two or more redundant power supplies. Each redundant power supply configured to receive input power from one or more power sources and configured to provide regulated output power to the load of the electronic device.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: International Business Machines CorporationInventors: Joseph W. Freeman, Randhir S. Malik, Derek Robertson -
Patent number: 6601164Abstract: A data processing system has one or more portions which are present or absent. The variant of the data processing system is automatically determined by means of an infra-red switch whose beam is broken when the one or more portions are absent and not being detected when said one or more portions are present and is not broken when the one or more portions are present. From the output of the infra-red switch, the variant of the data processing system is determined. The variant information is then stored in the data processing system.Type: GrantFiled: May 10, 2000Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventor: Derek Robertson
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Publication number: 20020015552Abstract: An optical wavelength router receives multiplexed bundles of wavelength channels from input optical fibers, processes the channels, and outputs the processed channels onto output optical fibers. The router separates one or more of the channels from the received bundles and couples the separated channels into a switching fabric. The remaining, i.e., pass-through, channels are multiplexed with wavelength-converted “add” signals and input into channel combiners. The outputs of the switching fabric may be “dropped,” or coupled to the channel combiners for multiplexing with the pass-through and the add channels. A second switching fabric may be interposed between the output ports of the channel combiners and the output fibers, and a redundant path through the router may be included for path fault protection.Type: ApplicationFiled: May 10, 2001Publication date: February 7, 2002Inventors: Gayle R. Link, Calvin J. Martin, Zelda Gills, Derek Robertson, Marcus W. Shute