Abstract: An apparatus includes coupling and supporting devices for floating and positioning a fixture to dock with another fixture. A coupling device is mounted on the fixture and coupled to an immediate plate using ball bearings to provide movements in X-Y directions as well as angular movements. The supporting device comprises a ball joint mounted between the immediate plate and a supporting plate to allow the fixture to be tilted. Sliding rods and a hinge are mounted on the supporting plate so that the fixture can be flipped over 180 degrees. Springs can be used instead of a ball joint. Sliding tracks and plates can also be used to provide movements in the X-Y directions. Guide devices each having a male guide member with a cone shaped head and a matched female guide member with a cone shaped void are used to guide the fixtures into positions for docking.

Abstract: An automatic tester uses a coarse timing subsystem and a formatter circuit to generate a first formatted waveform with coarse timing based on the information stored in a vector memory subsystem. The first formatted waveform is refined by a timing refiner circuit to form a second formatted waveform with precise timing. The timing refiner circuit includes a flip-flop device to re-synchronize and remove jitter in the first formatted waveform. A counter and/or shift register and vernier circuit in the timing refiner circuit then triggers the leading and trailing edges of the second formatted waveform with precise timing. The formatter circuit may be eliminated by using control signals of the memory devices in the vector memory subsystem to manipulate timing. The coarse timing subsystem may further be eliminated by providing sufficient range for the counters in the timing refiner circuit.

Abstract: A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (50.sub.1 -50.sub.M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (40.sub.1 and 40.sub.2) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.