Patents by Inventor Derek S. Swanson

Derek S. Swanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070657
    Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 30, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
  • Publication number: 20150097280
    Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
  • Publication number: 20150069624
    Abstract: Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second die located in the recessed portion, the second die including an active side facing the recessed surface of the first die and coupled thereto through the one or more through-die vias. In another embodiment, a method includes creating a recess on a first die having a first thickness, the recess having a depth smaller than the first thickness; coupling a second die having a second thickness greater than the depth to the recess; and reducing the thickness of the second die by an amount equal to or greater than a difference between the second thickness and the depth.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, Fonzell D. Martin, Derek S. Swanson
  • Patent number: 8754518
    Abstract: A semiconductor device includes a package substrate having a plurality of conductive elements, each of the conductive elements including a conductive trace and a bond finger positioned at an end of the conductive trace. The bond fingers can be arranged on the package substrate in at least three groups. A first group of the three groups can include a first number of the bond fingers. A third group of the three groups can include a third number of the bond fingers. A second group of the three groups can include an intermediate number of the bond fingers. The intermediate number is between the first and the third numbers. Spacing between the conductive elements along the length of the conductive elements is approximately the same.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Derek S. Swanson