Patents by Inventor Derek Sessions

Derek Sessions has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9529575
    Abstract: Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct). Moreover, the transformed shader program is amenable to optimization via existing compiler technology, and can be executed efficiently by CPU thread(s). A Dispatch call can be load-balanced on a CPU by assigning single or multiple CPU threads to execute thread blocks. In addition, the number of concurrently executing thread blocks do not overload the CPU.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 27, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
  • Patent number: 9430199
    Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
  • Patent number: 8806458
    Abstract: Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: August 12, 2014
    Assignee: Microsoft Corporation
    Inventors: Andy Glaister, Blaise Pascal Tine, Blake Pelton, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
  • Publication number: 20130219378
    Abstract: Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: Microsoft Corporation
    Inventors: Andy Glaister, Blaise Pascal Tine, Blake Pelton, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
  • Publication number: 20130215117
    Abstract: Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct). Moreover, the transformed shader program is amenable to optimization via existing compiler technology, and can be executed efficiently by CPU thread(s). A Dispatch call can be load-balanced on a CPU by assigning single or multiple CPU threads to execute thread blocks. In addition, the number of concurrently executing thread blocks do not overload the CPU.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: Microsoft Corporation
    Inventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
  • Publication number: 20130219377
    Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko