Abstract: A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

Abstract: A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

Abstract: Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

Abstract: Systems, methodologies, media, and other embodiments associated with data recovery are described. One exemplary system embodiment includes a sampling logic configured to sample data from a data line using a timing reference that is selectable from a plurality of timing reference signals. The system may also include a symbol history logic configured to track a symbol history of the data sampled by the sampling logic and a timing selection logic configured to select the timing reference used to sample the data based on the symbol history of the data to compensate for inter-symbol interference.